> + // FIXME: This should be accomplished programmatically by enumerating
> + // all PCI devices present in the system and computing
> + // PCI_INTERRUPT_LINE from PCI_INTERRUPT_PIN, the slot/position
> + // of the device, and the available host IRQs (for an example,
> + // see SeaBIOS pci_bios_init_devices() in src/fw/pciinit.c)
> + switch (HostBridgeDevId) {
> + case INTEL_82441_DEVICE_ID:
> + PciWrite8 (PCI_LIB_ADDRESS (0, 1, 2, 0x3c), 0x0b);
> + PciWrite8 (PCI_LIB_ADDRESS (0, 1, 3, 0x3c), 0x0a);
00:01.* is part of the northbridge and always present. This can be done
unconditionally and doesn't need to go into the "fixme" section.
> + PciWrite8 (PCI_LIB_ADDRESS (0, 3, 0, 0x3c), 0x0b);
> + PciWrite8 (PCI_LIB_ADDRESS (0, 4, 0, 0x3c), 0x0b);
> + PciWrite8 (PCI_LIB_ADDRESS (0, 5, 0, 0x3c), 0x0a);
That assumes device uses INTA and isn't multifunction. True for most
devices, ok as temporary stopgap. Maybe have a few more slots handled
that way.
> + break;
> + case INTEL_Q35_MCH_DEVICE_ID:
> + PciWrite8 (PCI_LIB_ADDRESS (0, 2, 0, 0x3c), 0x0b);
We likewise might want to handle a few more slots here.
> + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1d, 0, 0x3c), 0x0a);
> + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1d, 1, 0x3c), 0x0a);
> + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1d, 2, 0x3c), 0x0b);
> + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1d, 7, 0x3c), 0x0b);
Default usb devices (qemu -M q35 -usb). ok. Might want to add a
comment saying so.
> + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 2, 0x3c), 0x0a);
> + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 3, 0x3c), 0x0a);
This again is part of the northbridge and always present, so we can do
that unconditionally.
cheers,
Gerd
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