Unlike the one in PcAtChipsetPkg, our PciHostBridgeDxe module must handle address space translation. IO and MMIO addresses expressed in the respective apertures may be mapped to different bases in CPU address space, and in case of IO, they actually are.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <[email protected]> --- ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h | 2 ++ ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.c | 17 +++++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h index d724b6c..29008ad 100644 --- a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h +++ b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h @@ -458,6 +458,8 @@ typedef struct { UINT64 BusLimit; UINT64 MemLimit; UINT64 IoLimit; + UINT64 MemTranslation; + UINT64 IoTranslation; EFI_DEVICE_PATH_PROTOCOL *DevicePath; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; diff --git a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.c b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.c index 7c35e85..4c5decf 100644 --- a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.c @@ -640,11 +640,12 @@ RootBridgeConstructor ( PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol); // - // The host to pci bridge, the host memory and io addresses are - // direct mapped to pci addresses, so no need translate, set bases to 0. + // The host to pci bridge. // - PrivateData->MemBase = ResAperture->MemBase; - PrivateData->IoBase = ResAperture->IoBase; + PrivateData->MemBase = ResAperture->MemBase; + PrivateData->MemTranslation = ResAperture->MemTranslation; + PrivateData->IoBase = ResAperture->IoBase; + PrivateData->IoTranslation = ResAperture->IoTranslation; // // The host bridge only supports 32bit addressing for memory @@ -886,6 +887,7 @@ RootBridgeIoMemRW ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; UINT8 InStride; UINT8 OutStride; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; @@ -896,6 +898,9 @@ RootBridgeIoMemRW ( return Status; } + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + Address += PrivateData->MemTranslation; + InStride = mInStride[Width]; OutStride = mOutStride[Width]; OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); @@ -978,6 +983,7 @@ RootBridgeIoIoRW ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; UINT8 InStride; UINT8 OutStride; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; @@ -988,6 +994,9 @@ RootBridgeIoIoRW ( return Status; } + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + Address += PrivateData->IoTranslation; + InStride = mInStride[Width]; OutStride = mOutStride[Width]; OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); -- 1.8.3.1 ------------------------------------------------------------------------------ Dive into the World of Parallel Programming. The Go Parallel Website, sponsored by Intel and developed in partnership with Slashdot Media, is your hub for all things parallel software development, from weekly thought leadership blogs to news, videos, case studies, tutorials and more. Take a look and join the conversation now. http://goparallel.sourceforge.net/ _______________________________________________ edk2-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/edk2-devel
