Reviewed-By: Olivier Martin <[email protected]>

> -----Original Message-----
> From: Laszlo Ersek [mailto:[email protected]]
> Sent: 14 February 2015 22:02
> To: [email protected]; [email protected]; Peter Maydell; Ard
> Biesheuvel; Drew Jones; Wei Huang; Donald Dutile; Wei Liu
> Subject: [edk2] [PATCH 16/27] ArmVirtualizationPkg/PciHostBridgeDxe:
> allocate IO BARs top-down
> 
> Currently we allocate IO BARs bottom-up in the
> EfiPciHostBridgeAllocateResources phase of the enumeration.
> 
> > GCD:AddIoSpace(Base=0000000000000000,Length=0000000000010000)
> >   GcdIoType    = I/O
> >   Status = Success
> > GCDIoType  Range
> > ========== =================================
> > I/O        0000000000000000-000000000000FFFF
> 
> Because the IO aperture is based at zero, the first allocation happens
> to
> get the zero address. However, a zero address for a PCI BAR is
> considered
> unmapped; see eg.:
> 
> - <http://www.pcisig.com/reflector/msg00459.html>,
> 
> - the (new_addr == 0) part in QEMU, pci_bar_address() [hw/pci/pci.c]:
> 
>     new_addr = pci_get_long(d->config + bar) & ~(size - 1);
>     last_addr = new_addr + size - 1;
>     /* Check if 32 bit BAR wraps around explicitly.
>      * TODO: make priorities correct and remove this work around.
>      */
>     if (last_addr <= new_addr || new_addr == 0 || last_addr >=
> UINT32_MAX)
>     {
>         return PCI_BAR_UNMAPPED;
>     }
> 
> We can avoid this problem by allocating top-down in the IO aperture.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Laszlo Ersek <[email protected]>
> ---
>  ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.c |
> 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git
> a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.c
> b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.c
> index 973735a..635ecaa 100644
> ---
> a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.c
> +++
> b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.c
> @@ -382,8 +382,9 @@ NotifyPhase(
>                    BitsOfAlignment = 0;
>                  }
> 
> +                BaseAddress = mResAperture[0][0].IoLimit;
>                  Status = gDS->AllocateIoSpace (
> -                                EfiGcdAllocateAnySearchBottomUp,
> +                                EfiGcdAllocateMaxAddressSearchTopDown,
>                                  EfiGcdIoTypeIo,
>                                  BitsOfAlignment,
>                                  AddrLen,
> --
> 1.8.3.1
> 
> 
> 
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