Would you mind to move the new PCD definitions to ArmPlatformPkg/ArmPlatformPkg.dec. I had to introduce similar ones recently (code not public yet) that would be better to use the same ones.
> -----Original Message----- > From: Laszlo Ersek [mailto:[email protected]] > Sent: 14 February 2015 22:02 > To: [email protected]; [email protected]; Peter Maydell; Ard > Biesheuvel; Drew Jones; Wei Huang; Donald Dutile; Wei Liu > Subject: [edk2] [PATCH 06/27] ArmVirtualizationPkg/VirtFdtDxe: parse > "pci-host-ecam-generic" properties > > In the Linux kernel tree, > "Documentation/devicetree/bindings/pci/host-generic-pci.txt" describes > the > device tree bindings of a Generic PCI host controller. > > Recent QEMU patches from Alexander Graf implement such a controller on > the > "virt" machine type of qemu-system-(aarch64|arm): > > pcie@10000000 { > // > // (devfn<<8, 0, 0) PCI irq > // ---------------- ------- > interrupt-map-mask = <0x1800 0x0 0x0 0x7>; > > // gic irq > // (devfn<<8, 0, 0) pin+1 phandle (type, nr, > level) > // ---------------- ----- -------- ---------------- > - > interrupt-map = < 0x0 0x0 0x0 0x1 0x8001 0x0 0x3 0x4 > 0x0 0x0 0x0 0x2 0x8001 0x0 0x4 0x4 > 0x0 0x0 0x0 0x3 0x8001 0x0 0x5 0x4 > 0x0 0x0 0x0 0x4 0x8001 0x0 0x6 0x4 > 0x800 0x0 0x0 0x1 0x8001 0x0 0x4 0x4 > 0x800 0x0 0x0 0x2 0x8001 0x0 0x5 0x4 > 0x800 0x0 0x0 0x3 0x8001 0x0 0x6 0x4 > 0x800 0x0 0x0 0x4 0x8001 0x0 0x3 0x4 > 0x1000 0x0 0x0 0x1 0x8001 0x0 0x5 0x4 > 0x1000 0x0 0x0 0x2 0x8001 0x0 0x6 0x4 > 0x1000 0x0 0x0 0x3 0x8001 0x0 0x3 0x4 > 0x1000 0x0 0x0 0x4 0x8001 0x0 0x4 0x4 > 0x1800 0x0 0x0 0x1 0x8001 0x0 0x6 0x4 > 0x1800 0x0 0x0 0x2 0x8001 0x0 0x3 0x4 > 0x1800 0x0 0x0 0x3 0x8001 0x0 0x4 0x4 > 0x1800 0x0 0x0 0x4 0x8001 0x0 0x5 0x4>; > > #interrupt-cells = <0x1>; > > // > // child base cpu base > // type address address size > // --------- -------------- -------------- -------------- > ranges = <0x1000000 0x0 0x0 0x0 0x3eff0000 0x0 0x10000 > 0x2000000 0x0 0x10000000 0x0 0x10000000 0x0 > 0x2eff0000>; > > // > // PCIe config PCIe config > // space base space size > // -------------- ------------- > reg = <0x0 0x3f000000 0x0 0x1000000>; > > // > // allowed bus numbers; inclusive range > // > bus-range = <0x0 0xf>; > > #size-cells = <0x2>; > #address-cells = <0x3>; > device_type = "pci"; > compatible = "pci-host-ecam-generic"; > }; > > Parse those properties of the compatible="pci-host-ecam-generic" node > into > PCDs that are relevant for PCI enumeration in edk2. A PCD for the PCI > express config space base address already exists (controlling > MdePkg/Library/BasePciExpressLib); the others are introduced afresh. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Laszlo Ersek <[email protected]> > --- > ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.inf | 9 ++ > ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.c | 171 > ++++++++++++++++++-- > ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec | 20 > +++ > ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationQemu.dsc | 9 ++ > 4 files changed, 199 insertions(+), 10 deletions(-) > > diff --git > a/ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.inf > b/ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.inf > index 514ce2f..4bb3d24 100644 > --- a/ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.inf > +++ b/ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.inf > @@ -50,6 +50,15 @@ > gArmVirtualizationTokenSpaceGuid.PcdArmPsciMethod > gArmVirtualizationTokenSpaceGuid.PcdFwCfgSelectorAddress > gArmVirtualizationTokenSpaceGuid.PcdFwCfgDataAddress > + gArmVirtualizationTokenSpaceGuid.PcdPciBusMin > + gArmVirtualizationTokenSpaceGuid.PcdPciBusMax > + gArmVirtualizationTokenSpaceGuid.PcdPciIoBase > + gArmVirtualizationTokenSpaceGuid.PcdPciIoSize > + gArmVirtualizationTokenSpaceGuid.PcdPciIoTranslation > + gArmVirtualizationTokenSpaceGuid.PcdPciMmioBase > + gArmVirtualizationTokenSpaceGuid.PcdPciMmioSize > + gArmVirtualizationTokenSpaceGuid.PcdPciMmioTranslation > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress > gArmTokenSpaceGuid.PcdGicDistributorBase > gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase > gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum > diff --git > a/ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.c > b/ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.c > index 751864d..af21bab 100644 > --- a/ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.c > +++ b/ArmPlatformPkg/ArmVirtualizationPkg/VirtFdtDxe/VirtFdtDxe.c > @@ -46,23 +46,25 @@ typedef enum { > PropertyTypeTimer, > PropertyTypePsci, > PropertyTypeFwCfg, > + PropertyTypePciHost, > } PROPERTY_TYPE; > > typedef struct { > PROPERTY_TYPE Type; > - CHAR8 Compatible[20]; > + CHAR8 Compatible[32]; > } PROPERTY; > > STATIC CONST PROPERTY CompatibleProperties[] = { > - { PropertyTypeGic, "arm,cortex-a15-gic" }, > - { PropertyTypeRtc, "arm,pl031" }, > - { PropertyTypeVirtio, "virtio,mmio" }, > - { PropertyTypeUart, "arm,pl011" }, > - { PropertyTypeTimer, "arm,armv7-timer" }, > - { PropertyTypeTimer, "arm,armv8-timer" }, > - { PropertyTypePsci, "arm,psci-0.2" }, > - { PropertyTypeFwCfg, "qemu,fw-cfg-mmio" }, > - { PropertyTypeUnknown, "" } > + { PropertyTypeGic, "arm,cortex-a15-gic" }, > + { PropertyTypeRtc, "arm,pl031" }, > + { PropertyTypeVirtio, "virtio,mmio" }, > + { PropertyTypeUart, "arm,pl011" }, > + { PropertyTypeTimer, "arm,armv7-timer" }, > + { PropertyTypeTimer, "arm,armv8-timer" }, > + { PropertyTypePsci, "arm,psci-0.2" }, > + { PropertyTypeFwCfg, "qemu,fw-cfg-mmio" }, > + { PropertyTypePciHost, "pci-host-ecam-generic" }, > + { PropertyTypeUnknown, "" } > }; > > typedef struct { > @@ -96,6 +98,149 @@ GetTypeFromNode ( > return PropertyTypeUnknown; > } > > +// > +// We expect the "ranges" property of "pci-host-ecam-generic" to > consist of > +// records like this. > +// > +#pragma pack (1) > +typedef struct { > + UINT32 Type; > + UINT64 ChildBase; > + UINT64 CpuBase; > + UINT64 Size; > +} DTB_PCI_HOST_RANGE_RECORD; > +#pragma pack () > + > +#define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31 > +#define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30 > +#define DTB_PCI_HOST_RANGE_ALIASED BIT29 > +#define DTB_PCI_HOST_RANGE_MMIO32 BIT25 > +#define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24) > +#define DTB_PCI_HOST_RANGE_IO BIT24 > +#define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 > | BIT24) > + > +/** > + Process the device tree node describing the generic PCI host > controller. > + > + param[in] DeviceTreeBase Pointer to the device tree. > + > + param[in] Node Offset of the device tree node whose > "compatible" > + property is "pci-host-ecam-generic". > + > + param[in] RegProp Pointer to the "reg" property of Node. The > caller > + is responsible for ensuring that the size > of the > + property is 4 UINT32 cells. > + > + @retval EFI_SUCCESS Parsing successful, properties parsed > from Node > + have been stored in dynamic PCDs. > + > + @retval EFI_PROTOCOL_ERROR Parsing failed. PCDs are left unchanged. > +**/ > +STATIC > +EFI_STATUS > +EFIAPI > +ProcessPciHost ( > + IN CONST VOID *DeviceTreeBase, > + IN INT32 Node, > + IN CONST VOID *RegProp > + ) > +{ > + UINT64 ConfigBase, ConfigSize; > + CONST VOID *Prop; > + INT32 Len; > + UINT32 BusMin, BusMax; > + UINT32 RecordIdx; > + UINT64 IoBase, IoSize, IoTranslation; > + UINT64 MmioBase, MmioSize, MmioTranslation; > + > + // > + // Fetch the ECAM window. > + // > + ConfigBase = fdt64_to_cpu (((CONST UINT64 *)RegProp)[0]); > + ConfigSize = fdt64_to_cpu (((CONST UINT64 *)RegProp)[1]); > + > + // > + // Fetch the bus range (note: inclusive). > + // > + Prop = fdt_getprop (DeviceTreeBase, Node, "bus-range", &Len); > + if (Prop == NULL || Len != 2 * sizeof(UINT32)) { > + DEBUG ((EFI_D_ERROR, "%a: 'bus-range' not found or invalid\n", > + __FUNCTION__)); > + return EFI_PROTOCOL_ERROR; > + } > + BusMin = fdt32_to_cpu (((CONST UINT32 *)Prop)[0]); > + BusMax = fdt32_to_cpu (((CONST UINT32 *)Prop)[1]); > + > + // > + // Sanity check: the config space must accommodate all 4K register > bytes of > + // all 8 functions of all 32 devices of all buses. > + // > + if (BusMax < BusMin || BusMax - BusMin == MAX_UINT32 || > + DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < BusMax - BusMin + 1) > { > + DEBUG ((EFI_D_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n", > + __FUNCTION__)); > + return EFI_PROTOCOL_ERROR; > + } > + > + // > + // Iterate over "ranges". > + // > + Prop = fdt_getprop (DeviceTreeBase, Node, "ranges", &Len); > + if (Prop == NULL || Len == 0 || > + Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) { > + DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", > __FUNCTION__)); > + return EFI_PROTOCOL_ERROR; > + } > + > + IoSize = 0; > + MmioSize = 0; > + for (RecordIdx = 0; RecordIdx < Len / sizeof > (DTB_PCI_HOST_RANGE_RECORD); > + ++RecordIdx) { > + CONST DTB_PCI_HOST_RANGE_RECORD *Record; > + > + Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx; > + switch (fdt32_to_cpu (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) > { > + case DTB_PCI_HOST_RANGE_IO: > + IoBase = fdt64_to_cpu (Record->ChildBase); > + IoSize = fdt64_to_cpu (Record->Size); > + IoTranslation = fdt64_to_cpu (Record->CpuBase) - IoBase; > + break; > + > + case DTB_PCI_HOST_RANGE_MMIO32: > + case DTB_PCI_HOST_RANGE_MMIO64: > + MmioBase = fdt64_to_cpu (Record->ChildBase); > + MmioSize = fdt64_to_cpu (Record->Size); > + MmioTranslation = fdt64_to_cpu (Record->CpuBase) - MmioBase; > + break; > + } > + } > + if (IoSize == 0 || MmioSize == 0) { > + DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__, > + (IoSize == 0) ? "IO" : "MMIO")); > + return EFI_PROTOCOL_ERROR; > + } > + > + PcdSet64 (PcdPciExpressBaseAddress, ConfigBase); > + > + PcdSet32 (PcdPciBusMin, BusMin); > + PcdSet32 (PcdPciBusMax, BusMax); > + > + PcdSet64 (PcdPciIoBase, IoBase); > + PcdSet64 (PcdPciIoSize, IoSize); > + PcdSet64 (PcdPciIoTranslation, IoTranslation); > + > + PcdSet64 (PcdPciMmioBase, MmioBase); > + PcdSet64 (PcdPciMmioSize, MmioSize); > + PcdSet64 (PcdPciMmioTranslation, MmioTranslation); > + > + DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] " > + "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x%Lx\n", __FUNCTION__, > ConfigBase, > + ConfigSize, BusMin, BusMax, IoBase, IoSize, IoTranslation, > MmioBase, > + MmioSize, MmioTranslation)); > + return EFI_SUCCESS; > +} > + > + > EFI_STATUS > EFIAPI > InitializeVirtFdtDxe ( > @@ -167,6 +312,12 @@ InitializeVirtFdtDxe ( > (PropType == PropertyTypePsci)); > > switch (PropType) { > + case PropertyTypePciHost: > + ASSERT (Len == 2 * sizeof (UINT64)); > + Status = ProcessPciHost (DeviceTreeBase, Node, RegProp); > + ASSERT_EFI_ERROR (Status); > + break; > + > case PropertyTypeFwCfg: > ASSERT (Len == 2 * sizeof (UINT64)); > > diff --git > a/ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec > b/ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec > index 9941154..663858e 100644 > --- a/ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec > +++ b/ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec > @@ -56,3 +56,23 @@ > > > gArmVirtualizationTokenSpaceGuid.PcdFwCfgSelectorAddress|0x0|UINT64|0x0 > 0000004 > > gArmVirtualizationTokenSpaceGuid.PcdFwCfgDataAddress|0x0|UINT64|0x00000 > 005 > + > + # > + # Inclusive range of allowed PCI buses. > + # > + gArmVirtualizationTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000006 > + gArmVirtualizationTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x00000007 > + > + # > + # Bases, sizes and translation offsets of IO and MMIO spaces, > respectively. > + # Note that "IO" is just another MMIO range that simulates IO space, > there > + # are no special instructions to access it. In addition, the base > addresses > + # are address space relative; in order to get the physical address > for the > + # CPU, the translation value has to be added. > + # > + gArmVirtualizationTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000008 > + gArmVirtualizationTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000009 > + > gArmVirtualizationTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000 > 00a > + > gArmVirtualizationTokenSpaceGuid.PcdPciMmioBase|0x0|UINT64|0x0000000b > + > gArmVirtualizationTokenSpaceGuid.PcdPciMmioSize|0x0|UINT64|0x0000000c > + > gArmVirtualizationTokenSpaceGuid.PcdPciMmioTranslation|0x0|UINT64|0x000 > 0000d > diff --git > a/ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationQemu.dsc > b/ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationQemu.dsc > index 32c8deb..4368c40 100644 > --- a/ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationQemu.dsc > +++ b/ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationQemu.dsc > @@ -181,6 +181,15 @@ > > gArmVirtualizationTokenSpaceGuid.PcdFwCfgSelectorAddress|0x0 > gArmVirtualizationTokenSpaceGuid.PcdFwCfgDataAddress|0x0 > + gArmVirtualizationTokenSpaceGuid.PcdPciBusMin|0x0 > + gArmVirtualizationTokenSpaceGuid.PcdPciBusMax|0x0 > + gArmVirtualizationTokenSpaceGuid.PcdPciIoBase|0x0 > + gArmVirtualizationTokenSpaceGuid.PcdPciIoSize|0x0 > + gArmVirtualizationTokenSpaceGuid.PcdPciIoTranslation|0x0 > + gArmVirtualizationTokenSpaceGuid.PcdPciMmioBase|0x0 > + gArmVirtualizationTokenSpaceGuid.PcdPciMmioSize|0x0 > + gArmVirtualizationTokenSpaceGuid.PcdPciMmioTranslation|0x0 > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x0 > > gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3 > > -- > 1.8.3.1 > > > > ----------------------------------------------------------------------- > ------- > Dive into the World of Parallel Programming. The Go Parallel Website, > sponsored by Intel and developed in partnership with Slashdot Media, is > your > hub for all things parallel software development, from weekly thought > leadership blogs to news, videos, case studies, tutorials and more. > Take a > look and join the conversation now. http://goparallel.sourceforge.net/ > _______________________________________________ > edk2-devel mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/edk2-devel ------------------------------------------------------------------------------ Download BIRT iHub F-Type - The Free Enterprise-Grade BIRT Server from Actuate! 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