> -----Original Message-----
> From: Laszlo Ersek [mailto:[email protected]]
> Sent: 18 February 2015 21:08
> To: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Subject: [edk2] [PATCH v2 11/28] ArmVirtualizationPkg/PciHostBridgeDxe:
> translate addresses for IO and MMIO
> 
> Unlike the one in PcAtChipsetPkg, our PciHostBridgeDxe module must
> handle
> address space translation. IO and MMIO addresses expressed in the
> respective apertures may be mapped to different bases in CPU address
> space, and in case of IO, they actually are.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Laszlo Ersek <[email protected]>
> ---
>  ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h
> |  2 ++
>  ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.c
> | 17 +++++++++++++----
>  2 files changed, 15 insertions(+), 4 deletions(-)
> 
> diff --git
> a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h
> b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h
> index 19952a2..2b1ac58 100644
> ---
> a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h
> +++
> b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h
> @@ -458,6 +458,8 @@ typedef struct {
>    UINT64                 BusLimit;
>    UINT64                 MemLimit;
>    UINT64                 IoLimit;
> +  UINT64                 MemTranslation;
> +  UINT64                 IoTranslation;
> 
>    EFI_DEVICE_PATH_PROTOCOL                *DevicePath;
>    EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         Io;
> diff --git
> a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.
> c
> b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.
> c
> index 7c35e85..4c5decf 100644
> ---
> a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.
> c
> +++
> b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciRootBridgeIo.
> c
> @@ -640,11 +640,12 @@ RootBridgeConstructor (
>    PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS
> (Protocol);
> 
>    //
> -  // The host to pci bridge, the host memory and io addresses are
> -  // direct mapped to pci addresses, so no need translate, set bases
> to 0.
> +  // The host to pci bridge.
>    //
> -  PrivateData->MemBase = ResAperture->MemBase;
> -  PrivateData->IoBase  = ResAperture->IoBase;
> +  PrivateData->MemBase        = ResAperture->MemBase;
> +  PrivateData->MemTranslation = ResAperture->MemTranslation;
> +  PrivateData->IoBase         = ResAperture->IoBase;
> +  PrivateData->IoTranslation  = ResAperture->IoTranslation;
> 
>    //
>    // The host bridge only supports 32bit addressing for memory
> @@ -886,6 +887,7 @@ RootBridgeIoMemRW (
>    )
>  {
>    EFI_STATUS                             Status;
> +  PCI_ROOT_BRIDGE_INSTANCE               *PrivateData;
>    UINT8                                  InStride;
>    UINT8                                  OutStride;
>    EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  OperationWidth;
> @@ -896,6 +898,9 @@ RootBridgeIoMemRW (
>      return Status;
>    }
> 
> +  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
> +  Address += PrivateData->MemTranslation;
> +
>    InStride = mInStride[Width];
>    OutStride = mOutStride[Width];
>    OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width &
> 0x03);
> @@ -978,6 +983,7 @@ RootBridgeIoIoRW (
>    )
>  {
>    EFI_STATUS                             Status;
> +  PCI_ROOT_BRIDGE_INSTANCE               *PrivateData;
>    UINT8                                  InStride;
>    UINT8                                  OutStride;
>    EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  OperationWidth;
> @@ -988,6 +994,9 @@ RootBridgeIoIoRW (
>      return Status;
>    }
> 
> +  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
> +  Address += PrivateData->IoTranslation;

In case this patch still makes sense (related to the parallel discussion).
Would you mind to add a quick comment on the fact the operation supports
negative IoTranslation value?
It was this line that triggered the discussion about negative offset.


> +
>    InStride = mInStride[Width];
>    OutStride = mOutStride[Width];
>    OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width &
> 0x03);
> --
> 1.8.3.1
> 
> 
> 
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