Move platform specific macros to their own include files. In addition, define some new macros for register addresses (both PCI and IO) and register values (bits).
Cc: Gabriel Somlo <so...@cmu.edu> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <ler...@redhat.com> --- OvmfPkg/Include/IndustryStandard/I440FxPiix4.h | 40 +++++++++ OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 93 ++++++++++++++++++++ OvmfPkg/Include/OvmfPlatforms.h | 25 +----- 3 files changed, 136 insertions(+), 22 deletions(-) diff --git a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h new file mode 100644 index 0000000..8cbd685 --- /dev/null +++ b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h @@ -0,0 +1,40 @@ +/** @file + Various register numbers and value bits based on the following publications: + - Intel(R) datasheet 290549-001 + - Intel(R) datasheet 290562-001 + - Intel(R) datasheet 297654-006 + - Intel(R) datasheet 297738-017 + + Copyright (C) 2015, Red Hat, Inc. + Copyright (c) 2014, Gabriel L. Somlo <so...@cmu.edu> + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __I440FX_PIIX4_H__ +#define __I440FX_PIIX4_H__ + +#include <Library/PciLib.h> + +// +// Host Bridge Device ID (DID) value for I440FX +// +#define INTEL_82441_DEVICE_ID 0x1237 + +// +// B/D/F/Type: 0/1/3/PCI +// +#define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset)) + +#define PIIX4_PMBA 0x40 + +#define PIIX4_PMREGMISC 0x80 +#define PIIX4_PMREGMISC_PMIOSE BIT0 + +#endif diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h new file mode 100644 index 0000000..4f59a7c --- /dev/null +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -0,0 +1,93 @@ +/** @file + Various register numbers and value bits based on the following publications: + - Intel(R) datasheet 316966-002 + - Intel(R) datasheet 316972-004 + + Copyright (C) 2015, Red Hat, Inc. + Copyright (c) 2014, Gabriel L. Somlo <so...@cmu.edu> + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __Q35_MCH_ICH9_H__ +#define __Q35_MCH_ICH9_H__ + +#include <Library/PciLib.h> + +// +// Host Bridge Device ID (DID) value for Q35/MCH +// +#define INTEL_Q35_MCH_DEVICE_ID 0x29C0 + +// +// B/D/F/Type: 0/0/0/PCI +// +#define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset)) + +#define MCH_GGC 0x52 +#define MCH_GGC_IVD BIT1 + +#define MCH_SMRAM 0x9D +#define MCH_SMRAM_D_LCK BIT4 +#define MCH_SMRAM_G_SMRAME BIT3 + +#define MCH_ESMRAMC 0x9E +#define MCH_ESMRAMC_H_SMRAME BIT7 +#define MCH_ESMRAMC_E_SMERR BIT6 +#define MCH_ESMRAMC_SM_CACHE BIT5 +#define MCH_ESMRAMC_SM_L1 BIT4 +#define MCH_ESMRAMC_SM_L2 BIT3 +#define MCH_ESMRAMC_TSEG_8MB BIT2 +#define MCH_ESMRAMC_TSEG_2MB BIT1 +#define MCH_ESMRAMC_TSEG_1MB 0 +#define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1) +#define MCH_ESMRAMC_T_EN BIT0 + +#define MCH_GBSM 0xA4 +#define MCH_GBSM_MB_SHIFT 20 + +#define MCH_BGSM 0xA8 +#define MCH_BGSM_MB_SHIFT 20 + +#define MCH_TSEGMB 0xAC +#define MCH_TSEGMB_MB_SHIFT 20 + +#define MCH_TOLUD 0xB0 +#define MCH_TOLUD_MB_SHIFT 4 + +// +// B/D/F/Type: 0/0x1f/0/PCI +// +#define POWER_MGMT_REGISTER_Q35(Offset) \ + PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset)) + +#define ICH9_PMBASE 0x40 +#define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \ + BIT10 | BIT9 | BIT8 | BIT7) + +#define ICH9_ACPI_CNTL 0x44 +#define ICH9_ACPI_CNTL_ACPI_EN BIT7 + +#define ICH9_GEN_PMCON_1 0xA0 +#define ICH9_GEN_PMCON_1_SMI_LOCK BIT4 + +// +// IO ports +// +#define ICH9_APM_CNT 0xB2 +#define ICH9_APM_STS 0xB3 + +// +// IO ports relative to PMBASE +// +#define ICH9_PMBASE_OFS_SMI_EN 0x30 +#define ICH9_SMI_EN_APMC_EN BIT5 +#define ICH9_SMI_EN_GBL_SMI_EN BIT0 + +#endif diff --git a/OvmfPkg/Include/OvmfPlatforms.h b/OvmfPkg/Include/OvmfPlatforms.h index cf6e624..19f0adb 100644 --- a/OvmfPkg/Include/OvmfPlatforms.h +++ b/OvmfPkg/Include/OvmfPlatforms.h @@ -1,6 +1,7 @@ /** @file OVMF Platform definitions + Copyright (C) 2015, Red Hat, Inc. Copyright (c) 2014, Gabriel L. Somlo <so...@cmu.edu> This program and the accompanying materials are licensed and made @@ -17,12 +18,8 @@ #include <Library/PciLib.h> #include <IndustryStandard/Pci22.h> - -// -// Host Bridge Device ID (DID) values for PIIX4 and Q35/MCH -// -#define INTEL_82441_DEVICE_ID 0x1237 // PIIX4 -#define INTEL_Q35_MCH_DEVICE_ID 0x29C0 // Q35 +#include <IndustryStandard/Q35MchIch9.h> +#include <IndustryStandard/I440FxPiix4.h> // // OVMF Host Bridge DID Address @@ -30,20 +27,4 @@ #define OVMF_HOSTBRIDGE_DID \ PCI_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_OFFSET) -// -// Power Management Device and Function numbers for PIIX4 and Q35/MCH -// -#define OVMF_PM_DEVICE_PIIX4 0x01 -#define OVMF_PM_FUNC_PIIX4 0x03 -#define OVMF_PM_DEVICE_Q35 0x1f -#define OVMF_PM_FUNC_Q35 0x00 - -// -// Power Management Register access for PIIX4 and Q35/MCH -// -#define POWER_MGMT_REGISTER_PIIX4(Offset) \ - PCI_LIB_ADDRESS (0, OVMF_PM_DEVICE_PIIX4, OVMF_PM_FUNC_PIIX4, (Offset)) -#define POWER_MGMT_REGISTER_Q35(Offset) \ - PCI_LIB_ADDRESS (0, OVMF_PM_DEVICE_Q35, OVMF_PM_FUNC_Q35, (Offset)) - #endif -- 1.8.3.1 ------------------------------------------------------------------------------ One dashboard for servers and applications across Physical-Virtual-Cloud Widest out-of-the-box monitoring support with 50+ applications Performance metrics, stats and reports that give you Actionable Insights Deep dive visibility with transaction tracing using APM Insight. http://ad.doubleclick.net/ddm/clk/290420510;117567292;y _______________________________________________ edk2-devel mailing list edk2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/edk2-devel
