Oops, I have been doing the math and you are right. I missed few bits in my 
mask.

Reviewed-By: Olivier Martin <olivier.mar...@arm.com>


-----Original Message-----
From: Heyi Guo [mailto:heyi....@linaro.org]
Sent: 19 May 2015 03:24
To: Olivier Martin
Cc: edk2-devel@lists.sourceforge.net; leif.lindh...@linaro.org; 
ilias.bi...@linaro.org; Heyi Guo
Subject: [edk2] [PATCH] ArmPkg: Expand AArch64 address width to 48 bits

The VA address space has a maximum address width of 48 bits in
AArch64 state; 48 bits address width limit will provide better compatibility 
than 40 bits for future CPU.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi....@linaro.org>
---
 ArmPkg/Include/Chipset/AArch64Mmu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h 
b/ArmPkg/Include/Chipset/AArch64Mmu.h
index 77a96ec..2398ba2 100644
--- a/ArmPkg/Include/Chipset/AArch64Mmu.h
+++ b/ArmPkg/Include/Chipset/AArch64Mmu.h
@@ -51,8 +51,8 @@
 #define TT_ALIGNMENT_BLOCK_ENTRY                BIT12
 #define TT_ALIGNMENT_DESCRIPTION_TABLE          BIT12

-#define TT_ADDRESS_MASK_BLOCK_ENTRY             (0xFFFFFFFULL << 12)
-#define TT_ADDRESS_MASK_DESCRIPTION_TABLE       (0xFFFFFFFULL << 12)
+#define TT_ADDRESS_MASK_BLOCK_ENTRY             (0xFFFFFFFFFULL << 12)
+#define TT_ADDRESS_MASK_DESCRIPTION_TABLE       (0xFFFFFFFFFULL << 12)

 #define TT_TYPE_MASK                            0x3
 #define TT_TYPE_TABLE_ENTRY                     0x3
--
2.1.4


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