It looks like I found where the problem is: My IRSIM test file looks like this: | Test Register File
stepsize 20 | Set up vectors vector C c[1] c[0] vector B b[1] b[0] vector A a[1] a[0] vector wordC wordC1 wordC0 vector wordB wordB1 wordB0 vector wordA wordA1 wordA0 vector col0 sel0 sel0_b vector col1 sel1 sel1_b vector rw oe we set wordC 00 set wordB 00 set wordA 00 set col0 01 set col1 01 set rw 00 | Setup clocks clock phip 1 1 0 clock phis 1 0 1 clock phis_b 0 1 1 c | Write 0 in register 0. Assert wordC0, set C data to 00, assert col0, assert write enable. p set wordC 00 set rw 01 set C 01 set col0 10 set col1 01 p | We expect 01 on both the bit/bitb going upwards out of the I/O buffers. assert sense0 0 assert sense0_b 1 assert sense1 0 assert sense1_b 1 | We expect 01 on both teh bit/bib going upwards out of sense amplifiers. assert so0 0 assert so0_b 1 assert so1 0 assert so1_b 1 | Going through the column multiplexer, the first column should have the data. assert t0 0 assert t0_b 1 assert t2 0 assert t2_b 1 p I was setting wordC to 01 at the same time when the I/O buffer is driving the bitlines. This would activate the cell and most likely was causing contention. I think I need to figure out a way to set wordC to 01 a little later once the bitlines have been driven. If I set wordC 00 (i.e., no cell is activated for writing), I get the proper values on the bitlines and the assertions pan out. Wonder if there is a way in IRSIM to do that. --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [email protected] For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en -~----------~----~----~----~------~----~------~--~---
