At 09:08 PM 9/10/2010, you wrote:
I am currently writing a processor in VHDL and plan on specifying it
down to the gate level in stages using different entity
configurations. That way I can go from behavioral to gate in stages
and test along the way.
As I am writing all the low level gates myself is there a defined
set that need to be used to get a proper netlist for the Silicon
Compiler in Electric? I am a ways from being able to do anything
useful with the processor, but I do have a CORDIC sine/cosine
generator specified at the gate level that I would like to try and place/route.
I am going to go through the manuals again as I muddle through this,
but any pointers in getting a VHDL project into routed cells would
be really useful.
You need to make a layout library with an exact set of standard
cells. This is described in the manual:
http://www.staticfreesoft.com/jmanual/mchap09-12.html
Beware of Electric's VHDL compiler: it handles structural VHDL but
NOT behavioral VHDL. Many advanced constructs are not recognized.
-Steven Rubin
--
You received this message because you are subscribed to the Google Groups "Electric
VLSI Editor" group.
To post to this group, send email to [email protected].
To unsubscribe from this group, send email to
[email protected].
For more options, visit this group at
http://groups.google.com/group/electricvlsi?hl=en.
