Steven, Thanks. I saw the basic set in the manual and will start to work on those. Is it possible to extend the library? There are a couple of basic gates I would like to add like a 3 input xor/xnor and some nand gates that have active low inputs. If these could be added as "standard" it would reduce the number of layers in the logic.
Also, if I follow the tutorial on the CMOSedu site, will the standard set of design rules be portable to MOSIS or will I need to get a copy of the rules first. I have a copy of Weste & Harris that has the rules in table format but have not compared them to the rules in Electric. I was looking using the SCMOS or SUBM rules. I still have a ways to go before this is really important, but would like to start out in the right direction at least. Ed -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Steven Rubin Sent: Saturday, September 11, 2010 12:24 AM To: [email protected] Subject: Re: Silicon Compiler At 09:08 PM 9/10/2010, you wrote: >I am currently writing a processor in VHDL and plan on specifying it >down to the gate level in stages using different entity >configurations. That way I can go from behavioral to gate in stages >and test along the way. > >As I am writing all the low level gates myself is there a defined >set that need to be used to get a proper netlist for the Silicon >Compiler in Electric? I am a ways from being able to do anything >useful with the processor, but I do have a CORDIC sine/cosine >generator specified at the gate level that I would like to try and place/route. > >I am going to go through the manuals again as I muddle through this, >but any pointers in getting a VHDL project into routed cells would >be really useful. You need to make a layout library with an exact set of standard cells. This is described in the manual: http://www.staticfreesoft.com/jmanual/mchap09-12.html Beware of Electric's VHDL compiler: it handles structural VHDL but NOT behavioral VHDL. Many advanced constructs are not recognized. -Steven Rubin -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en. -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
