> >The default Electric technology, "mocmos" has all of the variations >of MOSIS rules (Deep, SCMOS, and Submicron). Use "Technology >Preferences" to change the technology characteristics. > >I don't know how easy it would be to add new standard cells to the >Silicon Compiler set in the manual. > >Finally, one other problem with the silicon compiler is that it is 15 >years old and dates to a time when standard cells were laid out in >rows with routing channels inbetween. Now routing goes on top and >there is no need for a separate channel. So the silicon compiler wastes space. > > -Steve
Thanks, I was looking at some of the labs and such that are available and it seems there is a mix of schematic and VHDL work that is done. For most of what I am doing at the moment I would probably stay with VHDL most of the way. I am not too worried size at the moment. For what I am doing it probably wouldn't matter too much. However, if I wanted to add rom/ram it probably would. For things that need higher density, is it better to do the standard cell -> library -> schematic and place it that way and let the router stitch it together? If I remember I can export a cell back out to VHDL for testing later. That way I can create the library components I want in the schematic view, have a cell, and VHDL code that mimics it for functional testing at the moment. Once I get a ways along I will start using the IRSIM to test a lot of the design. I would like to be able to stay with the ability to prove the design in an FPGA as long as possible though. I would like to have a little boot loader rom embedded into the design and need to ensure that is running. Once I have confidence in my ability to go from VHDL -> Electric -> VHDL & IRSIM testing then I will probably go whichever route is faster in placing larger constructs. I think at some point I will need to go to whichever way allows creating a library and having the software do some place and route for me. Looks like a little more research then sitting down with a large pot of coffee to start placing wells and arcs. What is the limit on IRSIM capability? Will it do something like a small 8 bit processor as in the MIPS 8 Bit core lab if the full instruction set were included? I reached the limit on the AE version of ModelSim when I tried to simulate the CORDIC at the gate level. I had to switch some entities back to behavioral to allow it to simulate. I will be switch back to SymphonyEDA to do the testing on this design. Ed -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
