Yes, I guess that the synthesis from behavioral VHDL/Verilog description is interesting feature for many users. But what is your suggestion ? Do you want to implement this feature or this is a request for somebody to implement ?
-Dima On Wed, Nov 10, 2010 at 6:09 PM, Alexandre Rusev <[email protected]>wrote: > Why don't to try to implement behavorial VHDL support basing on > sourcecode of VHDL-to-gates compiler (converter from behavioral to > schematic VHDL) > available in Alliance CAD tool? > (http://www-asim.lip6.fr/recherche/alliance/) > > As a first step their command line tool may be integrated with > electric VHDL-to-silicone compiler. After that the C-source could be > ported to Java. > > As compile-compiler for interpreting VHDL Metamata JavaCC may be used > for example. > > > -- > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To post to this group, send email to [email protected]. > To unsubscribe from this group, send email to > [email protected]<electricvlsi%[email protected]> > . > For more options, visit this group at > http://groups.google.com/group/electricvlsi?hl=en. > > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
