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• Re: Digest for [email protected] - 4 updates in 1 topic Alexandre Rusev
• LVS process Bárbaro Maykel López-Portilla Vigil
• Netlist (.net) in Electric VLSI Bárbaro Maykel López-Portilla Vigil
  • Re: Netlist (.net) in Electric VLSI Steven Rubin
  • Re: Netlist (.net) in Electric VLSI Bárbaro Maykel López-Portilla Vigil
  • Re: Netlist (.net) in Electric VLSI rjacobbaker
  • Re: Netlist (.net) in Electric VLSI Gavin
  • Re: Netlist (.net) in Electric VLSI Steven Rubin
  • Re: Netlist (.net) in Electric VLSI R. Jacob Baker
  • Re: Netlist (.net) in Electric VLSI Gavin
• Re: '' exception caught '' error when doing DRC for mocmostechnology R K Tiwary
  • Re: '' exception caught '' error when doing DRC for mocmostechnology Patrick Mendes
  • Re: '' exception caught '' error when doing DRC for mocmostechnology sudheer k Muhammed
  • Re: '' exception caught '' error when doing DRC for mocmostechnology Steven Rubin
  • Re: '' exception caught '' error when doing DRC for mocmostechnology Vikas Varshney
• '' exception caught '' error when doing DRC for mocmos technology Yaqub Mahnashi
  • Re: '' exception caught '' error when doing DRC for mocmos technology Patrick Mendes
  • Re: '' exception caught '' error when doing DRC for mocmos technology Yaqub Mahnashi
  • Re: '' exception caught '' error when doing DRC for mocmos technology Patrick Mendes
• Re: SkyWater130 Electric PDK Preview Adam Joseph
  • Re: SkyWater130 Electric PDK Preview Joselito Morallo
  • Re: SkyWater130 Electric PDK Preview Adam Joseph
  • Re: SkyWater130 Electric PDK Preview Steven Rubin
  • Re: SkyWater130 Electric PDK Preview Adam Megacz Joseph
• HiDPI scaling problem on Windows Ayan Banerjee
  • Re: HiDPI scaling problem on Windows Gavin
• SkyWater layers description issues Alexandre Rusev
• Electric LTSpice/NGSpice instructions for Linux (for those who asked recently) Alexandre Rusev
• SkyWater PDK Abel Joseph John
  • Re: SkyWater PDK Joselito Morallo
  • Re: SkyWater PDK Estevao Teixeira
  • Re: SkyWater PDK Joselito Morallo
  • Re: SkyWater PDK Joselito Morallo
  • Re: SkyWater PDK Abel Joseph John
  • Re: SkyWater PDK Joselito Morallo
  • Re: SkyWater PDK Patrick Mendes
  • Re: SkyWater PDK Steven Rubin
  • Re: SkyWater PDK Joselito Morallo
  • Re: SkyWater PDK Joselito Morallo
  • Re: SkyWater PDK Gavin
  • Re: SkyWater PDK Adam Joseph
  • Re: SkyWater PDK R K Tiwary
  • Re: SkyWater PDK Joselito Morallo
  • Re: SkyWater PDK Patrick Mendes
  • Re: Skywater PDK Adam Joseph
• 3D functionality matthew erhart
  • Re: 3D functionality Patrick Mendes
  • Re: 3D functionality Abhishek Bhandari
• URL: "Produce your own physical chips. For free. In the Open." Alexandre Rusev
• MPW services question Alexandre Rusev
  • Re: MPW services question Patrick Mendes
  • Re: MPW services question Mircea Stan
• FreePDK news: they are going to usability for fabrication Alexandre Rusev
• mocmos tech import problems with 350nm MOSIS SCN3ME SCN3ME_SUBM Alexandre Rusev
  • Re: mocmos tech import problems with 350nm MOSIS SCN3ME SCN3ME_SUBM Steven Rubin
• Want to learn and implement PLL Design lingraj hiremath
• i want to design a project with TSMC 40nm process khaled hussein
• Help with enhancement of layout generation using Silicon Compiler on Electric Patrick Mendes
  • Re: Help with enhancement of layout generation using Silicon Compiler on Electric Steven Rubin
  • Re: Help with enhancement of layout generation using Silicon Compiler on Electric Patrick Mendes
• On implementing PDK-s rules and tech description for Electric Alexandre Rusev
  • Re: On implementing PDK-s rules and tech description for Electric Travis Ayres
  • Re: On implementing PDK-s rules and tech description for Electric Mircea Stan
  • Re: On implementing PDK-s rules and tech description for Electric Joselito Morallo
• TSMC 45nm PDK lingraj hiremath
  • Re: TSMC 45nm PDK Gavin
  • Re: TSMC 45nm PDK lingraj hiremath
  • Re: TSMC 45nm PDK Joselito Morallo
  • Re: TSMC 45nm PDK Steven Rubin
  • Re: TSMC 45nm PDK lingraj hiremath
  • Re: TSMC 45nm PDK Joselito Morallo
  • Re: TSMC 45nm PDK lingraj hiremath
  • Re: TSMC 45nm PDK Travis Ayres
  • Required FinFET PDK Lakshman Chirumamilla
  • Re: Required FinFET PDK Gavin Abo
• Question on interconnect layers and metal rules Alexandre Rusev
• EDA tool to compare with Electric (Glade is free but not opensource) Alexandre Rusev
  • Re: EDA tool to compare with Electric (Glade is free but not opensource) Travis Ayres
  • Re: EDA tool to compare with Electric (Glade is free but not opensource) John Arthur Porche
  • Re: EDA tool to compare with Electric (Glade is free but not opensource) Travis Ayres
  • Re: EDA tool to compare with Electric (Glade is free but not opensource) John Arthur Porche
• how to add ASU 45nm technology node file in electric Shubham Gajbhiye
  • Re: how to add ASU 45nm technology node file in electric Gavin Abo
• Regarding the output of my 2-bit CLA carry chain laid out on Electric and simulated on LT Spice Naga Spandana Muppaneni
  • Re: Regarding the output of my 2-bit CLA carry chain laid out on Electric and simulated on LT Spice Naga Spandana Muppaneni
• Patch for issue 15187 suggested (surrogate implementation) Alexandre Rusev
• More on FreePDK Alexandre Rusev
  • Re: More on FreePDK Travis Ayres
• Cadence technology file (*.tf) to Electric xml techfile Oleksandr Parfionov
• Question on liberty file generation Alexandre Rusev
  • Re: Question on liberty file generation Gavin Abo
• rearranging the schematic or routing constraints Mustafa
  • Re: rearranging the schematic or routing constraints Steven Rubin
  • Re: rearranging the schematic or routing constraints Mustafa
• Strange windows appearing after schematic simulation in Electric Arvind Gupta
  • Re: Strange windows appearing after schematic simulation in Electric Gavin Abo
  • Re: Strange windows appearing after schematic simulation in Electric Arvind Gupta
  • Re: Strange windows appearing after schematic simulation in Electric Gavin Abo
• LTspice IV Unknown subcircuit called in David Teh
  • Re: LTspice IV Unknown subcircuit called in Gavin Abo
  • Re: LTspice IV Unknown subcircuit called in David Teh
• TSMC 180nm Technology Kim Cornett
  • Re: TSMC 180nm Technology Gavin Abo
• Re: Using Electric with commercial libraries and the IBM 65 nm process Kim Cornett
  • Re: Using Electric with commercial libraries and the IBM 65 nm process Gavin
  • Re: Using Electric with commercial libraries and the IBM 65 nm process Kim Cornett
  • Re: Using Electric with commercial libraries and the IBM 65 nm process Gavin Abo
• No simulation data error srikanth konde
  • Re: No simulation data error Gavin Abo
  • Re: No simulation data error R. Jacob Baker
  • Re: No simulation data error srikanth konde
• LTspice installed on Mac: run program and with args paths Rizwan
  • Re: LTspice installed on Mac: run program and with args paths Ashwin Balagopal S ee17d200
  • Re: LTspice installed on Mac: run program and with args paths Gavin Abo
  • Re: LTspice installed on Mac: run program and with args paths Colin Hart
  • Re: LTspice installed on Mac: run program and with args paths Rizwan
  • Re: LTspice installed on Mac: run program and with args paths Rizwan
• Verilog Code to Schematic and Layout Salar Parast
  • Re: Verilog Code to Schematic and Layout Gavin Abo
• Submitting patch to Electric build Alexandre Rusev
  • Re: Submitting patch to Electric build Dmitry Nadezhin
  • Re: Submitting patch to Electric build Dmitry Nadezhin
• Re: Digest for [email protected] - 6 updates in 4 topics Alexandre Rusev
• Setting Spice Model in ELECTRIC Naushad Alam
  • Re: Setting Spice Model in ELECTRIC Gavin Abo
• Low Pass Filter using different technologies Salar Parast
  • Re: Low Pass Filter using different technologies Gavin Abo
• Electric waveform window not working in batch mode Arvind Gupta
  • Re: Electric waveform window not working in batch mode Gavin Abo
• Developer training Steven Rubin
  • Re: Developer training Travis Ayres
  • Re: Developer training Steven Rubin
• Pdk Dr. Ahmad Mouri Zadeh
• bug?: fleeting ability to directly edit parameter-text on a node rb@ef
• Can I replay from log today? Or externally trigger Force-Save (of Force Save and Quit) to panic/*.jelib dir? rb-efabless
  • Re: Can I replay from log today? Or externally trigger Force-Save (of Force Save and Quit) to panic/*.jelib dir? Steven Rubin
• Integrating Electric and LTSpice ee17d200
  • Re: Integrating Electric and LTSpice Gavin Abo
• Issue Integrating Electric and LTSpice ee17d200
  • Re: Issue Integrating Electric and LTSpice Naushad Alam
  • Re: Issue Integrating Electric and LTSpice Gavin Abo
• Re: Digest for [email protected] - 6 updates in 1 topic Alexandre Rusev
  • Re: Digest for [email protected] - 6 updates in 1 topic Guru Murthy
  • Re: Digest for [email protected] - 6 updates in 1 topic Alexandre Rusev
• how instal electric in linux Guru Murthy
  • Re: how instal electric in linux Sanjeev Gupta
  • Re: how instal electric in linux Guru Murthy
  • Re: how instal electric in linux Guru Murthy
• Qflow Alexandre Rusev
• Re: Digest for [email protected] - 6 updates in 3 topics Alexandre Rusev
• Fabrication of chip through MOSIS enahorooriero
• MOSIS Fabrication Oriero Enahoro
  • Re: MOSIS Fabrication Gavin Abo
  • Re: MOSIS Fabrication Benjamin Reyes
  • MOSIS Fabrication Oriero Enahoro
  • MOSIS Fabrication Enahoro
• 45 nm Technology file Oriero Enahoro
  • 45 nm Technology file Colin Hart
  • Re: 45 nm Technology file Enas
• Netlist Salar Parast
  • Re: Netlist Gavin Abo
• Pulse generator Salar Parast
  • Re: Pulse generator Justin Spencer
  • Re: Pulse generator Justin Spencer
  • Re: Pulse generator Salar Parast
  • Re: Pulse generator Gavin Abo
  • Re: Pulse generator Dan White
  • Re: Pulse generator Salar Parast
• a useful site izmirli
• Power measurement-reg. abinayamurugesan.9
• Electric VLSI IRSIM allowed commands Andrea Bettati
  • Re: Electric VLSI IRSIM allowed commands Gavin Abo
  • Re: Electric VLSI IRSIM allowed commands Andrea Bettati
• Silicon Compiler Tutorial/Giude: from schmatic to layout Andrea Bettati
  • Re: Silicon Compiler Tutorial/Giude: from schmatic to layout Gavin Abo
  • Re: Silicon Compiler Tutorial/Giude: from schmatic to layout Andrea Bettati
• open source real chip design izmirli
  • Re: open source real chip design Sanjeev Gupta
  • Re: open source real chip design Maxim Cournoyer
  • Re: open source real chip design Travis Ayres
  • Re: open source real chip design Sanjeev Gupta
• Physical Design from Verilog File to synthesis - floorplanning - placement mqamar.msee16seecs via Electric VLSI Editor
• ELECTRIC VLSI for Floorplanning, placement, Routing from Verilog file mqamar.msee16seecs via Electric VLSI Editor
• Schematic Labels and Exports Steven Andryzcik
  • Re: Schematic Labels and Exports Steven Rubin
• Implement the circuit for NMOS common source amplifier P V N S VISWANATHA KASYAP
• Implement the circuit for NMOS common source amplifier with resistive load P V N S VISWANATHA KASYAP
• Re: operation region CMOS in LTSpice Gavin Abo
• mocmoc-cn technology DRC run problem Shazia Shakeel
• DRC run error for mocmos-cn technology Shazia Shakeel
  • Re: DRC run error for mocmos-cn technology Shazia Shakeel
  • Re: DRC run error for mocmos-cn technology Shazia Shakeel
  • Re: DRC run error for mocmos-cn technology Shazia Shakeel
• inverter library in electric f20150256
  • Re: inverter library in electric Gavin Abo
• problem in ltspice simupation sujan kanti
  • Re: problem in ltspice simupation sujan kanti
  • Re: problem in ltspice simupation Gavin Abo
  • Re: problem in ltspice simupation sujan kanti
  • Re: problem in ltspice simupation Paul Sujan Kanti

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