The project "Electric Alliance" on java.net is public now: http://java.net/projects/electric-alliance
-Dima On Tue, Nov 16, 2010 at 10:22 AM, Dmitry Nadezhin <[email protected] > wrote: > I created a project "Electric Alliance" on java.net with such a > description: > Electric and Alliance are names of two open source VLSI CAD systems. > This project evaluates project flow from VHDL behavioral description to > layout > using combination of Alliance and Electric tools. > > I invite anybody interested in this topic to join the project by emailing > me or Alexandre Rusev. > > The new projects on java.net are private by default. We shall request > [email protected] to make "Electric Alliance" public as soon as > we prepare minimal contents > on Web pages of this project. > > -Dima > > > On Thu, Nov 11, 2010 at 6:40 PM, Alexandre Rusev <[email protected]>wrote: > >> >> >> Dmitry Nadezhin wrote: >> > Yes, I guess that the synthesis from behavioral VHDL/Verilog description >> is >> > interesting feature for many users. >> > But what is your suggestion ? Do you want to implement this feature or >> this >> > is a request for somebody to implement ? >> >> I think that the right implementation would require of more than one >> person effort. >> I considered thinking about to do something ;) >> >> My "plan" includes following, yet I guess that several enhancemets are >> to be done with Electric code and tested independently from >> "Behavorial VHDL implementation": >> >> [1] Analyze the algorithms of mapping to gates used in Alliance CAD on >> respect to >> applicability for Electiric workflow, carry out experiments with >> compiling Alliance tool >> output in Electric. >> [2] Contrive an abstract interface appropriate bot for mapper-to-gates >> and mapper-to-techlibrary-gates. >> (I thing that taking into account mapping to technology library >> instead of simple gates >> is needed to support FPGA) >> [3] Design HDL parser (using JavaCC for example) and integrate it into >> Electric. >> First appropriate BNF file must be selected is to be translated >> to JavaCC language... >> (this is needed due to use the same parser for behavioral and >> schematic VHDL) >> [4] Extract Alliance mapper-to-gates algorithm and integrate it to >> newly introduced parser. >> [5] Integrate new parser with current implementation of Electric >> schematic VHDL to gates mapper >> >> >> [1] and [3] would be better to perform at first due to implement it >> taking into account rwhat is needed by Alliance and Electric >> algorithms >> >> > >> >> Alex >> >> -- >> You received this message because you are subscribed to the Google Groups >> "Electric VLSI Editor" group. >> To post to this group, send email to [email protected]. >> To unsubscribe from this group, send email to >> [email protected]<electricvlsi%[email protected]> >> . >> For more options, visit this group at >> http://groups.google.com/group/electricvlsi?hl=en. >> >> > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
