Wondering if you resolved this. I'm in the same position with TSMC 180nm On Friday, July 25, 2008 at 3:31:18 AM UTC-5, Scott L. wrote: > > Hi, > > I am a student trying layout a design to be fabricated through MOSIS. > I would like to use Electric to do my layout, but my university has > everything set up only for Cadence tools. I really only need electric > to do some hand layout, place and route my standard cells, and create > my schematics. I will use Calibre to do my DRC and LVS work (it uses > GDS II streams so it is not a big deal to import these from > Electric). > > My design will use commercial standard cells from ARM on IBM's 65 nm > process (CMOS10SF - to be exact). I have already signed non- > disclosure agreements with ARM and IBM to have access to this > information. > > I do not want to reinvent the wheel (nor do I have the time/energy) to > modify a technology library with all the new rules for the technology > file and do all the work to import the ARM standard cells into > Electric so I have a few questions... > > 1) Has anyone already updated the technology file to use Electric with > the IBM 65 nm library? > 2) Has anyone worked with importing commercially available standard > cells into Electric? I have the LEF files and everything that Cadence > requires to use the cells. > > Any help would be greatly appreciated. > > Thanks, > Scott >
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