On 02/06/2013 07:59 AM, Charles Steinkuehler wrote: > The GPIO pins can be written by the 700+ MHz ARM CPU, but they > apparently don't track changes that fast. Really, how deterministic > the pin updates can be seems more important than the ultimate > frequency, at least for step/dir control. Yes, TI is very tight about how this works, but it is fairly obvious the GPIO has very simple logic at the pads, mostly a pullup and pulldown resistor and switch, a FF with tri-state driver and a receiver. Then, they have a multiplexed logic component that handles 32 bits at a time, and sequentially processes each GPIO bank. On the OMAP3430 (I think that is the right part number for the Beagle Board) this is done every 240 ns.
There are also some bus bridges between the CPU and GPIO, so maybe that is where the 240 ns delay is. I don't understand the reason for this multiplexing, it doesn't seem that it would save very much area or power. But, with a 700+ MHz CPU, it is a bottleneck for embedded control applications. Jon ------------------------------------------------------------------------------ Free Next-Gen Firewall Hardware Offer Buy your Sophos next-gen firewall before the end March 2013 and get the hardware for free! Learn more. http://p.sf.net/sfu/sophos-d2d-feb _______________________________________________ Emc-developers mailing list Emc-developers@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-developers
