Hi, It occurred to me, while going through all the docs, that the RPI can do more than just SPI. There are actually enough GPIO pins to do bit-banged EPP as well. Even better, it turns out that you can have two EPP ports, two SPI ports, or one of each running simultaneously. This works without EPP and SPI biting each other if the pin-assignments are non-overlapping (EPP0+EPP1, SPI0+EPP1, SPI1+EPP0 or SPI0+SPI1 can operate in parallel and no mutex is needed).
The performance of EPP is similar to SPI (about 5 MByte/s). SPI has the advantage of fewer pins to do the connection. EPP has the advantage of a lower operating frequency. Although, SPI suffers from the round-trip delay and can write at ~5MB/s, but only read at 3..4MB/s. EPP actually has the potential to be faster if the firmware eases up on the imposed 200ns cycle-time. As an academic exercise, I went ahead and wrote a test-driver and emulated an EPP slave on some other hardware I had (pretending to be 7i43 and 7i90). Not a whole card emulation, but just enough to get the communication checked. It all seems to work quite well. So, anybody interested in a test drive? -- Greetings Bertho (disclaimers are disclaimed) ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ Emc-developers mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-developers
