On 06/20/2017 02:19 PM, andy pugh wrote: >> So, anybody interested in a test drive? > I think this is an interesting idea, and something I considered myself a > while ago. > I even made a bunch of PCBs to do the voltage level shifting: > https://goo.gl/photos/vFdUEhSiq6Ei448D8
Do you need the level-shifters? For the 7i90, the SPI lines seem to be 3.3V (attached directly to the FPGA) or the added propagation delay would kill the SPI transfer speed. So I think that all lines are actually 3.3V (but 5V tolerant). The CPLD on the 7i43 is used for 5V tolerance (stated in the manual under "EPP CONFIGURATION"). If the CPLD is not powered from 5V, then you would not need level-shifting as the i/o is at 3.3V. However, if you want long cables, then you do need to add buffers. I did the exercise of designing a PCB. It was designed to support both SPI and EPP using short flat-cables. See: http://media.vagrearg.org/rpi3-lcnc/pi-epp-s.png http://media.vagrearg.org/rpi3-lcnc/pi-epp.pdf (canceled the previous reply, message size exceeded on attachments; now replaced with links) > I wonder if there is a way to slot the virtual EPP port into a port > address, so that the existing drivers (such as Pico PPMC) can use them > without modification? It should be possible to write a kernel lp driver supporting EPP mode using bit-banging on the GPIOs. -- Greetings Bertho (disclaimers are disclaimed) ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ Emc-developers mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-developers
