Hi Max, It is important to qualify the board design when choosing an approach. I assume a high speed design (50+ MHz fundamental) which uses power and ground planes. For those that don't, the approach that you discuss would seem to be appropriate. For those that do, there may be other issues to consider. Did Van Doren's paper clearly state to which type of design the technique you describe applied? Several other papers that he has done are quite clear in making the distinction.
I am quoting from a paper entitled "Power Bus Decoupling on Multilayer Printed Circuit Boards" by Van Doren, Drewniak, Hubing, and Hockanson. Here is a quote from the "Conclusions" section (all emphasis in CAPS is mine). So that I don't present their conclusions out of context, I am giving you the entire conclusion section: "Unlike boards without internal power and ground planes, multilayer boards have a built in capacitance is a more effective source of current than surface decoupling capacitors at high frequencies. IN THE TIME DOMAIN, THIS MEANS THAT MOST OF THE INITIAL CURRENT TO A FAST SWITHING DEVICE IS PROVIDED BY THE INTERPLANE CAPACITANCE. ON PRINTED CIRCUIT BOARDS THAT DO NOT HAVE INTERNAL POWER AND GROUND PLANES, it is important to locate decoupling capacitors near to the active devices that they are intended to decouple. The capacitors nearest the active device are the primary source of high frequency current even at frequencies well above the capacitor's self-resonance frequency. HOWEVER, ON PRINTED CIRCUIT BOARDS THAT DO HAVE INTERNAL POWER AND GROUND PLANES, all decoupling capacitors are shared in the frequency range in which they are effective (typically below 200-300 MHz), AND THE LOCATION OF A DECOUPLING CAPACITOR ON THE BOARD IS RELATIVELY UNIMPORTANT. At frequencies above series resonance, the inductive reactance of decoupling capacitors on a multilayer board resonates with capacitance within and on the board resulting in undesirable peaks in the board impedance. Beyond the highest parallel-resonance frequency, adding decoupling capacitors on a multilayer board supply relatively little current to tha active devices and are therefore ineffective. REDUCING THE INDUCTANCE OF THE INTERCONNECTS IS PERHAPS THE BEST WAY TO GET ADDED DECOUPLING CAPACITORS TO BE EFFECTIVE AT HIGHER FREQUENCIES. Large vias or multiple vias within the capacitor bonding pads can be used to achieve interconnect inductances less than 1 nH. Using many decoupling capacitors with the same value and same interconnect inductance also increases the effective frequency range as indicated by Equations (5) and (9). DIFFERENT CIRCUITS AND DIFFERENT BOARD LAYOUTS MAY REQUIRE DIFFERENT DECOUPLING AND POWER DISTRIBUTION STRATEGIES. However, the results presented here indicate that existing multilayer board designs with typical interconnect inductances of 2 - 10 nH do not make effective use of all the added decoupling capacitors. Multilayer boards with a few nanofarads of interplane capacitance that have decoupling capacitors connected through a few nanohenires of inductance derive very little benefit from any added decoupling capacitors above approximately 100 - 200 MHz." I had the opportunity to meet with Dr. Todd Hubing of UMR (one of the authors of the above) for several hours at a previous job. I asked him at what point did they find that discrete capacitor placement was relatively unimportant at higher frequencies. He said that their research showed that with typical dielectrics on today's fabs, when the power and ground plane spacing goes below about 10 mils, capacitor placement is not as critical and a low inductance connection (i.e. vias) of the discrete caps to the power and ground plane become the dominant factor in the effectiveness of the decoupling circuit at lower frequencies. This suggests that the best design approach when using power and ground planes is to use adjacent layers in the stack for power and ground since even one additional layer of separation will usually put you over the 10 mil recommendation. At that point is is NOT necessary to place the decoupling caps at the power and ground pins of the IC but to put them where you've got the space to put in multiple or large vias to get the interconnect partial inductance below 1 nH. The interplane capacitance and capacitance designed within the IC package itself does the work at higher frequencies. Put another way, the plane partial inductance is a small percentage of the interconnect partial inductance for the discrete caps when VCC/GRD spacing is below 10 mils such that placement is no longer critical. This makes everyones job easier for a change! Regards, [email protected] PS: I am using the term partial inductance to represent the concept that it is a protion of the entire loop inductance required to calculate the response parameters of an LCR circuit. ---------- From: Max To: B.Ma Cc: emc-pstc; B.Gleason; mkelson Subject: Re: RFI Problems with Certified Computers List-Post: [email protected] Date: Friday, April 19, 1996 9:58AM %> %> %> Hi Ladies/Gentlemen, %> %> I have been reading with interest the discussion articles on this %> subject. Since Mike Violette 04/15/96 presented his opinion on VCC/GND %> plane layout in multilayer board, the discussion seems to be focused %> on PCB EMC design. Max Kelson 04/16/96 wrote: %> %> [snip] %> What this ferrite/cap configuration would do is to force the %> oscillator to draw all transient current from the capacitor. Or, in %> otherwords, the rest of the caps on the board would be unable to help %> provide fast-transient current because of the ferrite. This would %> keep the current loop (power AND GROUND) small and prevent it from %> infecting the rest of the board. The path for the transient current %> surges would be from the capacitor to the IC's power pin, out the %> IC's ground pin and back to the negative side of the capacitor (a %> relatively small loop). %> [snip] %> %> %> It might be worthwhile to pay attention to research work done by %> professors at the Univ. of Missouri-Rolla. In the article "Power Bus %> Decoupling on Multilayer Printed Circuit Board", IEEE Trans. on EMC, %> vol. 37, pp. 155-166, May 995, they wrote: %> %> [snip] %> VI. Conclusion. %> Unlike boards without internal power and ground planes, multilayer %> boards have a built-in capacitance that is a more effective source of %> current than surface decoupling capacitors at high frequencies. In the %> time-domain, this means that most of the initial current supplied to a %> fast switching device is provided by the interplane capacitance. %> [snip] %> %> %> Regards, %> Barry Ma %> %> I attended an EMC seminar conducted by Dr. Tom Van Doren on June 8, 1992 and then another one on March 23, 1995 by Dr. Van Doren, entitled "Circuit Board Layout to reduce Electromagnetic Emission and Susceptibility. It was amazing how much progress Dr. Van Doren had made on the general subject of controlling EMC on the board level between the two dates. In this seminar the importance of a low Zo with the DC power bus was discussed extensively and there was a lot of information on bypass capacitors also. These two subjects are really the leading edge topics for EMC control in the 90's, I think. One idea that Dr. Van Doren suggested during the seminar was to connect the bypass caps directly to the VCC and ground pins. This suggestion was given with the caveat that the physical geometries be within some critical spacing distances that he recommended. With the cap connected directly to VCC and ground, he also suggested a layout where traces go some distance before they are connected to the DC power and return planes. So, in otherwords, Dr Van Doren, an EMC professor, and Earl McCune, an RF communications consultant [1] have essentially arrived at the same conclusion, I think. They are both suggesting that the loop be minimized with a bypass capacitors and that a series impedance be added in the tap off the power plane. The only difference is that McCune recommends the use of a resistor, a low-Q inductor or a ferrite while Van Doren suggests using the natural impedance of circuit board traces to provide the impedance. The question that remains unanswered, I think, is at what frequencies is this method effective and will the capacitors be fast enough to provide the current, etc. This is an issue that needs a lot of research and one of the big problems is the dynamics in the capacitor industry and the lack of appropriate capacitor specifications. Dr. Van Doren, for example, provides some sample ESL figures, in one of his calculations, of 30 nH. In other calculation, he uses 100 nH. However, I don't think he is aware that there is at least one leading edge manufacturer (AVX) that is providing SMT MLC's with very low ESR's and ESL's. As I recall AVX makes some of these capacitors with ESL's as low as about 0.7 nH. Ultimately, I think the answer has to be to use these low inductance caps to provide for an IC's high (relatively speaking) transient current requirements and use built-in caps to provide the higher frequency, lower current requirements (as mentioned previously). I highly recommend Dr. Van Doren's seminars, BTW. The information that he provides is new, and interesting and exciting. Dr. Van Doren, incidently, provides his email address in his seminar book and, as I recall, I did send him one question once and got a polite and prompt response. Max [email protected] Max Kelson Peripherals Engineer Evans & Sutherland Computer Corp. [1] "Ground-Current Control Enhances Dynamic Range in High-Speed Circuits, Earl McCune, MSEE, RF Communications Consulting, EDN, January 19, 1995.
