Mike, This all sounds about right to me too (see comment below).
Comments: I have not seen data that proves the VCC island around oscillators is better or worse than a solid plane. Some processor manufacturers recommend this approach for the PLL power and return references, and they recommend that filtering be used between +3.3V and PLL +3.3V. I have tried both approaches on the same design and there didn't seem to be any difference between product performance or EMI from the processor board, so it didn't prove anything one way or the other. I am not in favor of an island with no necked down area (a complete island) because the retun current loops are difficult to mimimize or mange (nature does a better job!). With a necked down area, the case can be made that as long as ALL signals are routed over the necked area and the neck is wide enough (ie, the signals effectively "see" an infinite return plane), then loop areas can be managed. Obviously, the wider the neck, the lower impedance the return path (the more the signal lines see what looks like an infinite return plane), and the easier it is to route. But this leads to the limiting case that the widest neck is no neck at all, which is exactly what one has with a solid ground/VCC plane. So theoretically and philisophically, the case can be made that a solid plane is still the ideal method of minimizing ground bounce and common mode noise from signal return currents. Looking at it another way, the island approach sets up the situation of a noisy area (the oscillator island) electrically separated from the quiet area (the main VCC/ground plane) by an impedance (the ferrites or narrow necked down area). This is the model for a dipole structure, which is what we want to avoid. This is also the model for the noisy logic ground/clean chassis ground design used in a number of products. I have used this approach successfully at a prior company but always wondered if my designs would have been even better by defining only one return reference and referencing to chassis everywhere I could. Back to the specific case of the oscillator island, it could be that the unintended parasitic capacitance that Mike refers to is the only thing that saves one's butt when one tries to implement the island approach. I would suspect that the majority of the parasitic capacitance is formed from the voltage plane to the logic return plane and back to the island voltage plane rather than directly from the voltage plane to the island voltage plane since geometrically, this is where all of the plate area and the smallest plate spacing are created. Since I am a victim of the 50/50 rule (I am probably wrong as often as right), it would be nice to see some empirical data to back up this conjecture. Anyone know of a good study by objective researchers which proves the concept one way or another? Regards, [email protected] ---------- From: mikev To: mkelson Cc: emc-pstc Subject: Re: RFI problems with PC's ... List-Post: [email protected] Date: Monday, April 15, 1996 1:35PM Hi Max, Multi-point grounding of PCB to metal chassis is a good idea. The beneficial effect of the multi-point connection of the PCB to a metal chassis is to reduce the net impedance associated with the return currents for signals flowing on the PCB. The impedance decrease provides a lower voltage generated across the printed circuit board, thus reducing the common mode present on the various circuit nodes on the board. This is especially critical as frequencies rise, regardless of the concern often raised about (the red herring of) "ground loops". In fact, one of my pet peeves, as it were, are "low noise designs" that use "isolation"--segregated Vcc/0V structures--to keep noise from coupling between areas of the circuitry. It is common to see high frequency circuits on PCBs separated with ferrite beads and having isolated, DC-coupled 0V planes. Often, the oscillator is designed with its own Vcc/0V island. The fallacies of this approach are as follows: 1. Intentionally segregating the Vcc/0V structures drives up the impedance in return paths, creating RF voltages at the isolation element (be it a ferrite bead in Vcc or a 'necked down' area in the 0V plane). The net effect is to produce a common mode voltages in series with every signal line that is associated with "isolated" area. When you route a conductor off of the isolated area, this common mode voltage is a high frequency "ripple" on the conductor. 2. At RF, the circuits are coupled anyway! The parasitic capacitance between circuits negates the notion of high frequency isolation. Of the sixty or so examples of this "design" implementation we have seen over the past year or two, the performance during radiated emissions is always troublesome. I'd welcome comments on this subject.
