Hi! We are looking for some advice on copper thieving on the PCB. The concern is the EMC impact of the floating copper. Anyone is willing to share his/her experience on the best configuration for high percentage of copper coverage and low EMI at the same time ? Refer to the post to SI list by my colleague Dorin on this issue.
Any advice on this will be greatly appreciated. Regards Perry Qu
--- Begin Message ---Hi, I am working now on the copper balance issue we have on our PCBs. On the outer layer beneath the converter a copper surface is required (E shielding) which generates the copper balance issue on that particular layer and also throughout the stack up. Thus, the unpopulated copper space is filled with square or circle floating copper surfaces separated in-between. These squares are overlapping throughout the stack up. The question: what is the best copper geometry, its dimension and the spacing between these geometries ?. Copper balance requires as much copper as possible but EMC wants no floating copper and very weak coupling between noisy areas such as converter and any functional digital area. Your help is really appreciated, Dorin **** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****
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