Hi all, I could have sworn that I read somewhere in EN 61010-1 that creepage distances on internal layers of "void free" PCB boards were reduced from the normal distances. For the life of me, I can't find the statement.
I also seem to remember that there was no hard, fast number given. So, my question is three fold. 1. Where is this statement? 2. Is it true that the creepage is reduced for interal layers (as compared to surface layers)? 3. If it is reduced, where do I find a table, or some actual values to use? As always, the wisdom of the group members is appreciated. Thanks, Chris Maxwell | Design Engineer - Optical Division email [email protected] | dir +1 315 266 5128 | fax +1 315 797 8024 NetTest | 6 Rhoads Drive, Utica, NY 13502 | USA web www.nettest.com | tel +1 315 797 4449 | ------------------------------------------- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: [email protected] with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: [email protected] Dave Heald: [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on "browse" and then "emc-pstc mailing list"
