EN 600065 for audio and video equipment judges
that the creepage between traces on a coated
PCB is non existent.....

As you may see, many standards do not have the
same opinion about the subject.

Regards,
 
Gert Gremmen, (Ing)

ce-test, qualified testing
 
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>>-----Original Message-----
>>From: [email protected]
>>[mailto:[email protected]]On Behalf Of [email protected]
>>Sent: Friday, February 01, 2002 6:41 PM
>>To: [email protected]
>>Cc: [email protected]
>>Subject: RE: Pollution Degree vs. Creapage Distance
>>
>>
>>
>>Thanks for the response and yes I was referring to EN60950. My 
>>apologies for not stating that in my message.
>>
>>I guess I was thinking that solder mask might be considered 
>>"enclosed" . Obviously the solder mask would not qualify as 
>>hermetically sealed or an approved insulating compound. Just 
>>trying to understand the Pollution degree 1 criteria. Am I to 
>>understand that only approved coatings constitutes "enclosed"?
>>
>>Thanks
>>
>>
>>Rick
>>
>>-----Original Message-----
>>From: Ron Pickard [mailto:[email protected]]
>>Sent: Friday, February 01, 2002 9:22 AM
>>To: Rick Busche
>>Cc: [email protected]
>>Subject: Re: Pollution Degree vs. Creapage Distance
>>
>>
>>
>>Hi Rick,
>>
>>I am assuming (ugh) that you are referring to EN60950 2nd 
>>Edition. If so, clause 2.9.6 clearly
>>addresses your question by requiring hermetic sealing or such 
>>enclosing to prevent the ingress of
>>dirt and/or moisture. IMHO, solder mask does not and cannot 
>>provide this type of protection and,
>>therefore, cannot be used as such.
>>
>>And, as for your question, "Why are the secondary circuit spacing 
>>requirements based on a primary
>>input voltage?". Look into Annex ZB of the above standard and 
>>then to the  reference clause 6.2.1.2.
>>Your answer is there as it relates to TNV circuits.
>>
>>Again, this is assuming that you were referring to the above standard.
>>
>>I hope this helps.
>>
>>Best regards,
>>
>>Ron Pickard
>>[email protected]
>>
>>
>>
>>
>>                                                                  
>>                                                          
>>                    [email protected]                                
>>                                                          
>>                    Sent by:                       To:     
>>[email protected]                                      
>>                    owner-emc-pstc@majordom        cc:            
>>                                                          
>>                    o.ieee.org                     Subject:     
>>Pollution Degree vs. Creapage Distance                      
>>                                                                  
>>                                                          
>>                                                                  
>>                                                          
>>                    01/31/02 01:01 PM                             
>>                                                          
>>                    Please respond to                             
>>                                                          
>>                    rbusche                                       
>>                                                          
>>                                                                  
>>                                                          
>>                                                                  
>>                                                          
>>
>>
>>
>>
>>
>>
>>I am wading through the creapage and clearance requirements for 
>>secondary circuits using the values
>>in tables 5 and 6. It becomes very apparent that the creapage 
>>distances become quite large when you
>>assume material group IIIb (CTI). For operational insulation, 
>>this might be 2-3X the clearance
>>values. My question to the group is:
>>
>>Does the application of a solder mask allow for a change from 
>>pollution degree 2 to pollution degree
>>1?  I understand that conformal coating requires significant 
>>testing when used to reduce spacings
>>per table 7, but in this case I am only asking if solder mask can 
>>be used to improve the pollution
>>concern.
>>
>>Assuming this is NOT the case, are there any other practical 
>>suggestions? Cutting slots in
>>multilayer cards is a bit tricky.  I can live with 0.7mm of 
>>clearance, but 2.5 mm (operational) or
>>5.0 (reinforced) of creapage is a bit difficult on a densely 
>>populated power supply.
>>
>>One last question. Why are the secondary circuit spacing 
>>requirements based on a primary input
>>voltage?
>>
>>Thanks
>>
>>Rick Busche
>>E&S
>>[email protected]
>>
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>>-------------------------------------------
>>This message is from the IEEE EMC Society Product Safety
>>Technical Committee emc-pstc discussion list.
>>
>>Visit our web site at:  http://www.ewh.ieee.org/soc/emcs/pstc/
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>>All emc-pstc postings are archived and searchable on the web at:
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