Kim, Here's how I would do it. Note that I'm assuming that we're dealing with SELV circuits here and your concern is SI/EMC on circuit packs for a shelf system. Safety grounding is another issue entirely.
First screws: I'd use split washers with flat beneath (if lock washers at all) to protect your surface. Screw/washer materials selection should be anti-corrosive and compatible with the surface finish of your PCB. Loctite or equivalent should be available applied to the screw tips from the screw supplier - this will ensure you don't get loctite on any of your contact surfaces. Now the hard to explain part - pads I would recommend flexibility on the pad end. In my earlier days at a test lab, I saw way too many products fail when either *all of the standoffs* or *one/none/few of the standoffs* (take your pick) were connected to digital ground. When we cut traces/removed mounting screws/made ground connections to nearby caps/etc..., the EMC problems would often go away. BUT then a respin was in order - and then manufacturing test - and then DVT - and then a compliance retest - and what if it made something else worse? At any rate, you're a month off schedule (minimum). Instead I would recommend surface layer pads and unplated holes for your standoffs with one or more DNI (or installed if that's your thing) components bridging the pads to digital ground. Pad size should be slightly larger than the mating surface diameter. This is a common practice these days in the telecom arena and will allow flexibility without respinning your board. If a problem is found in the lab that can be attributed to a grounding issue, it is simple to change the population of the DNI components to achieve a passing result that also has acceptable signal integrity (hopefully you're using differential signalling anyway for anything really fast). The best part about this method is that it is easy to convince your designers (who will undoubtedly be devoted to a certain grounding practice) to take this approach since the default population can reflect their current grounding ideology. For implementation of the above, I would stick with fairly wide SMT resistors - I found that 1812 zero ohm resistors and low value capacitors (220-2000pF range) are readily available. Remember to use VERY SHORT and relatively wide (3W rule) traces on the pad/component trace. For the digital ground end of the component, I would have more than one via (to dgnd) attached to the pad to minimize inductance to ground. Get creative to address card insertion ESD drain. And here is what it all comes down to: The worst thing that could happen is that manufacturing would have to change the component population for new production and retrofit the existing products. This gets particularly rewarding when a whole bunch of product is already made and you can just change components instead of scrapping the whole lot. (OK, it's not the worst thing....) I think I explained this clearly (?) If you have questions, feel free to ask. Keep in mind this is just my view on a topic where opinions and practices vary wildly (and are often accompanied by good results from all sides) Best Regards, Dave Heald (currently an unemployed victim of the telecom market but looking) This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: [email protected] with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: [email protected] Dave Heald: [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] Archive is being moved, we will announce when it is back on-line. All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc
