Hello Group - I've been away for a couple years but just now rejoined. I have some questions about analog versus digital ground planes and thought this would be the best place to review the topic. I have a design where I would like to keep one ground plane for both the analog and the digital logic but would like to hear the pros and cons to see if I am making a mistake. The application is a power distribution quality meter that must ignore High EMI exposure beyond the EN61000-6-2 levels. For example the meter must meet ANSI C37.90.2 in the new 20V/M level (with AM mod)
Let me describe the present layout. * Main board is an 8 layer PCB - dimensions ~ 182mm square. * Top layer copper pour is common. * Power PC core with bus running at 66MHz. * Two ADCs, one on left and one on right side of board, feed Ti DSP through serial links. * Physically the Digital components reside in the center of the board. * Power Supply is a plug in board perpendicular to the Main board . * 3.3 and 1.8V for Power PC, DSP and ADCs is created by buck regulator at bottom of board. * The ADCs are 6 channel sigma delta sampling at ~ 30Khz. * The 6 channels on the right measure line voltage through 2M ohm series resistors through load resistor to common in a single ended fashion. * The 6 channels on the left measure current through a (CT) Current transformer in a differential mode. * The CT Cww is less than 1pf and there are options for a ~ 90 ohm @ 100 MHz Ferrite beads on the CT primaries if necessary * So both the Voltage and Current measurements are high impedance through a wide frequency range. * Only Analog circuitry exists on the field side of the ADCs. * The ADCs share the digital 3.3V+ but is filtered through ferrite beads. * The ADCs have provisions for a separate Analog and Digital Common connection but I was planning on leaving these connected. With the above configuration I have been told that the ADCs Analog section will see the digital noise back to the buck regulators and this will degrade my analog readings. I have been told that I ought to create a separate return path to the 3.3V PS source to avoid this digital pollution. I am concerned that this will create a large loop antenna effect that will be an issue with a number of the high frequency EMI tests. About the only way I would be comfortable with a separate analog common plane would be to use a small SIP DC:DC PS up near the ADCs. In that way the Analog source would not have to travel any significant distance and would not be polluted by the digital circuitry. I have seen successful competitive products that do not separate the analog and digital commons. Your thoughts and reflections on best practice here would be greatly appreciated. Regards Chris Wells This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ieee-pses.org/ To cancel your subscription, send mail to: [email protected] with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: [email protected] Dave Heald: [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc
