In order not to oversimplify the issue, I will post some more information in a few days on risetimes and ESD voltages, some of which David Pommerenke mentioned if I can dig up the references. I just found one from 1991 in my library by Andy Hish and others.
It appears to me that to get a fast risetime spike at 10 kV, for instance, one has to work at it to get the arc length small. Some of the work by Andy Hish and others shows a dependence on the shape and symmetry of the discharge point. The point I would like to make is that these conditions rarely exist for the instance where one is plugging in a device, such as a flash memory card, into a receptacle like a card reader. It is difficult to do this fast (slow means longer arc length and longer risetimes). Other connector related discharges are likely similar. I did not make that clear in my original posting. I have taken a number of these kind of discharges and have not seen a sub-nanosecond rise at 8 kV yet because of the nature trying to discharge through a device as above. Sometimes I see the vestige of a leading edge spike and other times not, but not anything like the contact discharge event. Doug Doug Smith wrote: > Hi John, > > Companies are ignoring the device standards and requiring IEC 61000-4-2 > it be applied to devices they purchase even though not appropriate. The > issue is not likely to go away and will have to be dealt with. > > I have helped a number of my clients with this issue over the last few > years and the problem seems to be growing with time. > > Doug > > John Woodgate wrote: > >> In message <[email protected]>, dated Mon, 4 Sep 2006, Doug >> Smith <[email protected]> writes >> >>> There is a LOT of work to apply that standard to devices, much more >>> than the filtering I wrote about. There is no guidance in the >>> standard as to how to apply the discharge and how it is applied will >>> almost completely determine the results (other pins grounded or >>> ungrounded, if grounded how, and much more). If someone says their >>> device passes this test, the statement is meaningless at this point >>> unless the test method is documented. >> >> >> >> ESD immunity of semiconductors is a matter for the subcommittees of >> IEC TC47. A search on the public part of the IEC web site would >> perhaps indicate what is being done in this field already. > > -- ___ _ Doug Smith \ / ) P.O. Box 1457 ========= Los Gatos, CA 95031-1457 _ / \ / \ _ TEL/FAX: 408-356-4186/358-3799 / /\ \ ] / /\ \ Mobile: 408-858-4528 | q-----( ) | o | Email: [email protected] \ _ / ] \ _ / Website: http://www.dsmith.org - This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. Website: http://www.ieee-pses.org/ To post a message to the list, send your e-mail to [email protected] Instructions: http://listserv.ieee.org/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas [email protected] Mike Cantwell [email protected] For policy questions, send mail to: Jim Bacher: [email protected] David Heald: [email protected] All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc ______________________________________________________________________ This email has been scanned by the MessageLabs Email Security System. For more information please visit http://www.messagelabs.com/email ______________________________________________________________________
