As Amund says impedance is important. If your traces transition to different layers, did you maintain the correct impedance on all the layers?
One of the more common reasons for having issues is not dealing with the signal return current. It is not noted on the schematics, so it is usually overlooked during layout. It is hard for a lot of designers to see the issue as they do the layout. The signal return current path needs to form a transmission line / microstrip with the signal trace. Otherwise the signal trace is an antenna, which is not what you want. On Oct 15, 2016 2:26 AM, "Amund Westin" <[email protected]> wrote: > > LVDS issues … exactly the same lenght / impedance on all I/O lines and add common mode chokes on all lines aswell. > > > > Best regards > > Amund > > > > > - ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. To post a message to the list, send your e-mail to <[email protected]> All emc-pstc postings are archived and searchable on the web at: http://www.ieee-pses.org/emc-pstc.html Attachments are not permitted but the IEEE PSES Online Communities site at http://product-compliance.oc.ieee.org/ can be used for graphics (in well-used formats), large files, etc. Website: http://www.ieee-pses.org/ Instructions: http://www.ieee-pses.org/list.html (including how to unsubscribe) List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas <[email protected]> Mike Cantwell <[email protected]> For policy questions, send mail to: Jim Bacher: <[email protected]> David Heald: <[email protected]>
