Peter,

Great news. Will you be able to intermix steppers and PWMs on a single
board? If I understand correctly your statement on PWM, that should be
adequate for my needs. For my immediate project, I need three axes of
steppers and one unidirectional PWM (no encoder) with a frequency between
5Khz and 25Khz. 

I also recently received a development m5i20 board for this project, and
would be glad to help out with the EMC driver, testing, or anywhere else I
can assist.

Regards,
Eric

> Finally had a bit of free time to work on this. Still needs 
> testing and more features but here whats there so far:
> 
> 12 step gens. Each stepgen is 28 bit DDS + FIFO + 
> preset/residue clear logic
> 
> Step gens overlaid on basic I/O port, Step generators can be 
> individually enabled, or I/O pins left as simple I/O. So for 
> example if the stepgens are all disabled you have a 72 bit I/O port.
> 
> Step/DIR or quadature output selectable per generator.
> 
> Step gens are buffered (16 deep x 32 bit wide FIFOs each). 
> This means that real time is not required (at least for step 
> generation), For example at a basic clock of 8 MHz and a 
> frame size (frame size is how many additions are done to step 
> generator DDS per FIFO entry) of 8000, the step gen will 
> consume one FIFO entry per mSec. Since the FIFOs are 16 deep, 
> if we use interrupts or just poll the FIFOhalf full register 
> the interrupt latency or minimum polling time would ge 8 mSec 
> (125 Hz).
> 
> 
> Also the basic local bus interface has been changed to be 32 
> bit memory only, and has support for burst transfer mode.
> 
> 
> Things to do:
> 
> Add quadrature counters (probably just graft in existing one)
> 
> Add simplified PWM gens (no fancy signed/unsigned modes)
> 
> Add SPI channels (for general use plus for our I/O expander 
> and 7I41 stepper 
> interface use SPI)


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