Sebastian Kuzminsky wrote: > > > If the encoder counter provides only the number of edges seen since > startup (or since some reset event), then it's really hard to estimate > velocity well - it'll be quantised and crunchy (though as you say, maybe > filtering could help). > Yup, that is what my boards do right now. They do have a fast clock (1 MHz for digital filtering) but the FPGAs run at 10 MHz (old boards) and 40 MHz (newest ones). But, I hate to make a major modification if there is a decent way to do what we need in the PC. Maybe we can't, though. Once the information is lost, it can't be reconstructed. It just seems like 1000 samples/second OUGHT to be fast enough. My Allen-Bradley 7320 control had a 100 Hz servo cycle, and it worked fine, although clearly not as high a bandwidth as EMC can now provide.
Jon ------------------------------------------------------------------------------ This SF.net email is sponsored by: High Quality Requirements in a Collaborative Environment. Download a free trial of Rational Requirements Composer Now! http://p.sf.net/sfu/www-ibm-com _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
