Roland Jollivet wrote: > Hi all > > I'm trying to figure something out; > > With a servo type system using quadrature feedback, I see that "*the EMC ini > file uses two variables, FERROR and MIN_FERROR to define acceptable > following error for each axis. Think of MIN_FERROR as the following error > allowed at very low velocity and FERROR as the distance allowed during rapid > moves*." > > Now I know that each system has it's own intrinsic resolution, and that > machines move at different speeds, and that the CPU and read-update speed > has an effect, but considering that each encoder is read a number of times a > second; > > Surely there is no need to have a 32 bit counter? A 16 bit counter should > suffice? With a machine having 1u encoder resolution, the max count before > roll-over would correspond to a FERROR of around 32000 counts, or 32mm > You have conflated two distinct concepts here - encoder resolution and following error. Following error calculations have nothing to do with the encoder counter width, they're done in floating point after the hardware counters have been extended to whatever the driver wants (32 or 64 bits). > Considering a pretty fast G0 traverse of say 40m/min, then 32mm is traversed > in 48ms, plenty of time to get an update. > Look at it in terms of count rates vs servo rates: a fast encoder can do a few MHz, and emc typically runs the servo loop at 1 or more kHz. That leaves a few kCounts per servo cycle, more or less. So a 13 bit signed counter is probably large enough, and 16 bits is comfortably large in most situations. > So what I'm wondering is why do the Mesa cards use 32 bit counters for the > encoders? > > Would a 16bit counter not suffice? It just seems that there is a lot of time > spent reading redundant numbers from encoders, and that things could be > simplified with 16 bits. > There is almost no time spent reading "redundant" data. On the PCI cards, a 32-bit read takes the same or less time than a smaller width read. As explained elsewhere, the counter itself is only 16 bits, and you don't save anything by reducing that to 13 or 14 bits, since you still have to read two bytes to get the count.
- Steve ------------------------------------------------------------------------------ The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
