On May 5, 2012, at 8:14 PM, jeshua wrote: > 'pcils -v' reveals: > > 08:00.1 Non-VGA unclassified device: Oxford Semiconductor Ltd OX16PCI954 > (Quad 16950 UART) function 1 (parallel port) (rev 01) > Subsystem: Oxford Semiconductor Ltd Device 0000 > Flags: medium devsel, IRQ 18 > I/O ports at c050 [size=8] > I/O ports at c040 [size=8] > I/O ports at c000 [size=32]
I am looking at the data sheet for that chip: http://www.datasheetarchive.com/OX16PCI952-datasheet.html# It states on page 52: To use the Enhanced Parallel Port (‘EPP’) mode, the mode field of the Extended Control Register (ECR[7:5]) must be set to ‘100’ using the negotiation steps as defined by the IEEE1284 specification … The register set is compatible with the Microsoft(R) register definition. Assuming that the upper block is located 400h above the lower block, the EPP registers are found at offset 000-007h and 400-402h. Does anyone know what that actually means? Its a bit over my head. Thanks, Jeshua Lacock Founder/Engineer 3DTOPO Incorporated <http://3DTOPO.com> Phone: 208.462.4171 ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
