On Tue, 16 May 2017, Bertho Stultiens wrote: > Date: Tue, 16 May 2017 21:03:00 +0200 > From: Bertho Stultiens <ber...@vagrearg.org> > Reply-To: "Enhanced Machine Controller (EMC)" > <emc-users@lists.sourceforge.net> > To: "Enhanced Machine Controller (EMC)" <emc-users@lists.sourceforge.net> > Subject: Re: [Emc-users] switching to a slower spi driver to see if it works, > > On 05/16/2017 08:33 PM, Peter C. Wallace wrote: >> 50 MHz will work if everything is terminated correctly and if the RSPI timing >> is correct. (It may require using a SPI late data sample option if the RSPI >> hardware has that option) >> >> Correct series termination of RSPI outputs (130 Ohm total for 0.050" flat >> cable) depends on the output impedance of the RSPI outputs so there's no >> guarantee that the added 87 ohms is correct (this may also depend on RSPI >> output drive strength settings if such things exist on the RSPI) > > Well, in theory, that is true. I suspect that there is a phase-reversal > problem at these high frequencies. The probe of the scope adds just > enough capacity to delay the signal by a fraction. > > At 50MHz clock, you have a phase margin of <10ns. This time is consumed by: > - the wire-connection (~2ns per meter for copper), > - the round-trip in the slave tranceiver (the 7i90 SPI interface), > - the RPI buffers and SPI tranceiver. > > Lets assume that the wire, including PCB traces etc., takes 1ns > (roundtrip for 25 cm). The RPI buffers and shift register are probably > around 2ns and a bit more if it contains a glitch-filter. The 7i90 > interface has both input buffer, an output buffer and at least one > flip-flip propagation delay. My guess is that it would be about 0.5ns + > 0.5ns + 2ns. > > That brings the grand total to 6ns, which is at 60% of the phase margin. > This is an optimistic estimation where I specifically disregarded setup- > and hold-times, which make things much worse. Assuming setup- and > hold-margins on both ends (round-trip) of 0.5ns means adding another > 2ns, resulting in 8ns total time and 80% of the phase margin. This is > getting close to the failure point. > > Adding just a bit of capacity at the wrong place will make the signal > (seemingly) slower because the flanks are less steep (as seen on the > scope). This is enough to cause the system to fail. > > This also means that you cannot add external line-buffers on the lines. > These would simply add to much delay at these frequencies (something > like 6...10ns). Unfortunately, SPI is a synchronous and timing-bound > propocol and cannot tolerate phase reversal. > > > -- > Greetings Bertho > > (disclaimers are disclaimed) > > ------------------------------------------------------------------------------ > Check out the vibrant tech community on one of the world's most > engaging tech sites, Slashdot.org! http://sdm.link/slashdot > _______________________________________________ > Emc-users mailing list > Emc-users@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/emc-users >
All fine except that Gene said that slowing the clock (with added capacitance) made the interface work. If this were a clock --> read data timing issue, slowing the clock edges with added capacitance would make things worse. So I think its more likely a signal integrity issue, though as you say 50 MHz is probably pushing it. I've run the 7I90 slave SPI interface for weeks at 50 MHz with a FPGA master, but the FPGA master has the "late sample read data" option, not sure the RSPI has this or if its used Peter Wallace Mesa Electronics ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
