On Thursday 18 July 2019 19:59:41 Nicklas Karlsson wrote: > On Thu, 18 Jul 2019 23:07:08 +0100 > > andy pugh <[email protected]> wrote: > > On Thu, 18 Jul 2019 at 22:01, Nicklas Karlsson > > <[email protected]> > > > > wrote: > > > It seems by no suprise writing real time to data to file within > > > real time task have a negative impact on likelihood of real time > > > delay. > > > > With RTAI and kernel modules I don't think that is is even possible. > > > > I tried non blocking fcntl(...) function and O_NONBLOCK flag without > > > > > success. Adding some kind of buffer in for example shared memory > > > between written by real time task and let another lower priority > > > task write is a solution > > > > Take a look at how streamer and hal_streamer do exactly this. > > Yes. They do it with a FIFO and the FIFO is what I need. > > Have done FIFO in embedded Micro controller with similar purpose > before and used two "counters" to keep track of position within > buffer, properly implemented I think it works perfect if it is known > one process may interrupt the other but not the opposite as have been > the case, if the FIFO get full oldest value is overwritten which in > many cases is a good way to handle the situation in case there it not > enough time available. > > > Nicklas Karlsson
It occurs to me that an spi sort of driver on the pi4 might be able to drive the serial interface of something like the 7i76. This of course isn't truly practical because in the case of the 5i25 driving the 7i76, its the 5i25 supplying the fawncy stuff like stepgens and encoders, or at least thats how I understand it. The 7i90hd is a nice piece of hardware, fully able to be blown all the pot by one pulse from any noise source thats over +5 volts or below -.3 volts, so in order to use it one must add 3 7i42TA's, which work flawlessly while bringing the cost of an interface for the portless micros to above $200. It also brings the size up to at least 80% of a D525mw motherboard What we need is a 7i90hd board hat that contains the stuff from the TA's that sits directly on the 7i90. And then write our own rpspi, but make several variations such that the compiler can make several versions, using the headers unique to that particular gpio core, so it would be usable on most any of these things with a broadcom gpio core. The spi can support several channels by multiplexing the CS signals but I don't see any advantage to that complexity, and there is no innate improvement in the latency by doing so because of only one data pin. So theres 2 practical ways to interface to the pi4. 1. use one of the two usb3 ports, or 2. the gigabit ethernet port, using the wifi for utility networking if you can keep it locked down and the neighbors out of it. My pi3's radio is disabled because of that. A scan typically finds from 3 to 7 other signals, with 3 of them at 5 9's or better. Locked down, they are just noise to me. So, how likely is it that we already have the hardware, at a reasonable cost, to do 1 or 2 above? Cheers, Gene Heskett -- "There are four boxes to be used in defense of liberty: soap, ballot, jury, and ammo. Please use in that order." -Ed Howdershelt (Author) If we desire respect for the law, we must first make the law respectable. - Louis D. Brandeis Genes Web page <http://geneslinuxbox.net:6309/gene> _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
