On 16-11-2010 1:41, Thorsten Schnebeck wrote:
Am Montag, 15. November 2010, um 17:23:35 schrieb Maarten Burghout:
On 15-11-2010 15:52, Thorsten Schnebeck wrote:
just as a side node. You know that you need a µC controlling the
FB1111-014X SPI slave that runs Beckhoffs slave sample code or your
own adaption of the ethercat protocol stack? Only the
32-BIT-IO-FB1111-0142 type runs without further µC assistance.
Does this also hold when Device Emulation (see notes at AL control
register 0x0120) is enables, like I did (and didn't mention in my
earlier message)?
Ah, ok - that should work with reprogramming the eeprom for changing register
0x0140 - but I do not know how etherlab master handles the Error Indication
Acknowledge (see Sect. I - 10.1.2 in the ET1100 datasheet) and if this strange
resistor pdi configurator on the FB1111-0141 makes any problems.
Well, from what I can see the slave ends up in PREOP state after
power-up, and is in OP state when I run my modified 'user' example
design. The slave no longer indicates an error state when queried like
'ethercat slaves'.
However, my process data still does not end up in on of the registers at
the slave. My guess is that, given that no PDO entries are predefined
for a SPI slave, configuration as such fails (yet does not trigger a
warning or error message at the master-side).
Why would an SPI slave _not_ require a PDO entry mapping, whereas a uC-
or digital-I/O slave do?
Interestingly, at the ETG forum (subforum: Slave Devices, topic:
Adresses/Index for PDOs?) one 'Subrat Nayak' seems to try to implement
exactly the same. Are we both on a dead trail?
At this moment, we are aiming for a 1kHz control loop. Given a PWM value
represented by a 16-bit word, and an encoder value in 32-bit
representation, I'd think SPI (running at 5MHz at the moment, could be
increased to 20MHz if necessary) would be able to handle that.
That should work. You get the frame and a DC interrupt. Pipe the frame down to
the µC, process your inner control stuff, change the PWM and pipe the result up
to the ESC.
That's the idea exactly! Just some research into stability etc. for a
configuration in which the controller side (running the master stack)
has little or no influence on the handling of data at the plant side
(where the slave resides). No rocket science with tough spec's and
requirements...
If you have deeper knowledge in integrating your own PDI settings via CoE in
slave sample code (SSC) I would really like to hear from you. SSC is a little
monster ;-)
I've never seen (excerpts of) the Slave Sample Code myself. Behind my
EtherCAT slave I have a FPGA board, programmed with some OpenCores and
own work to read and write over the SPI PDI, without synchronizing to
the EtherCAT slave. I /thought/ that would do the job for me.
So in conclusion:
- why aren't there any PDO entries specified for a SPI slave?
- when put in Device Emulation mode, does the slave need any
configuration (one-shot or periodically) over the PDI?
Kind regards,
Maarten Burghout
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