On Mon, Nov 23, 2009 at 10:46:13AM -0800, Thao Hoang wrote: > Hi there. > > I'm trying to use flashrom and although the program can detect both my > chipset and my flash part (which are both tested & supported), the erase > routine fails. (Although I don't think it even erase since the content read > after this failure was the same and the board does boot up properly.) What > do you think is going on? Do you think it's something with my mainboard (per > some of the discussion I have seen?) > > Here is what I get when I do a write.... Thanks also for all the good work! > > r...@slax:/home/user/flashrom_folder/flashrom_unrelease# ./flashrom -f -w > backup.rom > flashrom v0.9.1-runknown > No coreboot table found. > Found chipset "Intel ICH7M", enabling flash write... OK. > This chipset supports the following protocols: LPC,FWH. > Calibrating delay loop... OK. > Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. > Flash image seems to be a legacy BIOS. Disabling checks. > Writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, > failed byte count from 0x00000000- 0x0000ffff: 0x13de > ERASE FAILED! > ERASE FAILED! > ERASE FAILED! > ERASE FAILED! > FAILED! > Your flash chip is in an unknown state. > Get help on IRC at irc.freenode.net (channel #flashrom) or > mail [email protected]! > ------------------------------------------------------------------------------- > DO NOT REBOOT OR POWEROFF!
Patch attached. Please reply with: Acked-by: Thao Hoang <[email protected]> when this works ok. Luc Verhaegen.
>From 7c33a83c47d8f097d210a49787816f9fbba008ac Mon Sep 17 00:00:00 2001 From: Luc Verhaegen <[email protected]> Date: Wed, 23 Dec 2009 03:46:21 +0100 Subject: [PATCH] Boards: Add iBase MB899. Signed-off-by: Luc Verhaegen <[email protected]> --- board_enable.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 763a58b..09efb97 100644 --- a/board_enable.c +++ b/board_enable.c @@ -852,6 +852,14 @@ static int intel_ich_gpio23_raise(const char *name) } /** + * Suited for IBase MB899: i945GM + ICH7. + */ +static int intel_ich_gpio26_raise(const char *name) +{ + return intel_ich_gpio_set(26, 1); +} + +/** * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. */ static int board_acorp_6a815epd(const char *name) @@ -1199,6 +1207,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", it87xx_probe_spi_flash}, {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", it87xx_probe_spi_flash}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, "hp", "dl145_g3", "HP", "DL145 G3", board_hp_dl145_g3_enable}, + {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, "ibase", "mb899", "iBASE", "MB899", intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, "IBM", "x3455", board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, "Intel", "D201GLY", wbsio_check_for_spi}, {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, "iwill", "dk8_htx", "IWILL", "DK8-HTX", w83627hf_gpio24_raise_2e}, -- 1.6.0.2
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