Add Nvidia nForce MCP61/MCP65/MCP67/MCP78S/MCP73/MCP79 SPI flashing support.
This code is totally untested and may fry your flash chip, explode mysteriously and abduct your dog. Do NOT try to read/write/erase with this code until we know that it behaves correctly. Logs from "flashrom -V" on all newer Nvidia nForce chipsets appreciated. This patch depends on my RayeR SPIPGM patch I sent a few minutes ago, Message-ID: <[email protected]> and available at http://patchwork.coreboot.org/patch/1401/ The code will be compiled in automatically if the internal programmer is enabled (which is the default). Signed-off-by: Carl-Daniel Hailfinger <[email protected]> diff generated by interdiff diff -u flashrom-bitbang_spi_rayer/flash.h flashrom-bitbang_spi_nvidia_mcp/flash.h --- flashrom-bitbang_spi_rayer/flash.h (Arbeitskopie) +++ flashrom-bitbang_spi_nvidia_mcp/flash.h (Arbeitskopie) @@ -132,6 +132,11 @@ #if RAYER_BITBANG_SPI_SUPPORT == 1 BITBANG_SPI_MASTER_RAYER, #endif +#if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) + BITBANG_SPI_MASTER_MCP, +#endif +#endif BITBANG_SPI_INVALID /* This must always be the last entry. */ }; @@ -527,6 +532,18 @@ int rayer_bitbang_get_miso(void); #endif +/* mcp6x_spi.c */ +#if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) +extern void *mcp6x_spibar; +int mcp6x_spi_init(void); +void mcp6x_bitbang_set_cs(int val); +void mcp6x_bitbang_set_sck(int val); +void mcp6x_bitbang_set_mosi(int val); +int mcp6x_bitbang_get_miso(void); +#endif +#endif + /* bitbang_spi.c */ extern int bitbang_spi_half_period; extern const struct bitbang_spi_master_entry bitbang_spi_master_table[]; @@ -633,6 +650,7 @@ SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, + SPI_CONTROLLER_MCP6X_BITBANG, #endif #endif #if FT2232_SPI_SUPPORT == 1 diff -u flashrom-bitbang_spi_rayer/spi25.c flashrom-bitbang_spi_nvidia_mcp/spi25.c --- flashrom-bitbang_spi_rayer/spi25.c (Arbeitskopie) +++ flashrom-bitbang_spi_nvidia_mcp/spi25.c (Arbeitskopie) @@ -178,6 +178,7 @@ case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: + case SPI_CONTROLLER_MCP6X_BITBANG: #endif #endif #if FT2232_SPI_SUPPORT == 1 diff -u flashrom-bitbang_spi_rayer/bitbang_spi.c flashrom-bitbang_spi_nvidia_mcp/bitbang_spi.c --- flashrom-bitbang_spi_rayer/bitbang_spi.c (Arbeitskopie) +++ flashrom-bitbang_spi_nvidia_mcp/bitbang_spi.c (Arbeitskopie) @@ -40,6 +40,18 @@ .get_miso = rayer_bitbang_get_miso, }, #endif + +#if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) + { + .set_cs = mcp6x_bitbang_set_cs, + .set_sck = mcp6x_bitbang_set_sck, + .set_mosi = mcp6x_bitbang_set_mosi, + .get_miso = mcp6x_bitbang_get_miso, + }, +#endif +#endif + {}, /* This entry corresponds to SPI_BITBANG_INVALID. */ }; diff -u flashrom-bitbang_spi_rayer/spi.c flashrom-bitbang_spi_nvidia_mcp/spi.c --- flashrom-bitbang_spi_rayer/spi.c (Arbeitskopie) +++ flashrom-bitbang_spi_nvidia_mcp/spi.c (Arbeitskopie) @@ -84,6 +84,13 @@ .read = wbsio_spi_read, .write_256 = wbsio_spi_write_1, }, + + { /* SPI_CONTROLLER_MCP6X_BITBANG */ + .command = bitbang_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = bitbang_spi_read, + .write_256 = bitbang_spi_write_256, + }, #endif #endif diff -u flashrom-bitbang_spi_rayer/Makefile flashrom-bitbang_spi_nvidia_mcp/Makefile --- flashrom-bitbang_spi_rayer/Makefile (Arbeitskopie) +++ flashrom-bitbang_spi_nvidia_mcp/Makefile (Arbeitskopie) @@ -92,8 +92,12 @@ ifeq ($(CONFIG_RAYER_BITBANG_SPI), yes) CONFIG_BITBANG_SPI = yes else +ifeq ($(CONFIG_INTERNAL), yes) +CONFIG_BITBANG_SPI = yes +else CONFIG_BITBANG_SPI ?= no endif +endif # Always enable 3Com NICs for now. CONFIG_NIC3COM ?= yes @@ -133,7 +137,7 @@ FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o # FIXME: The PROGRAMMER_OBJS below should only be included on x86. -PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o +PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o NEED_PCI := yes endif only in patch2: unchanged: --- flashrom-bitbang_spi_nvidia_mcp/chipset_enable.c (Revision 1013) +++ flashrom-bitbang_spi_nvidia_mcp/chipset_enable.c (Arbeitskopie) @@ -1063,10 +1063,8 @@ { int ret = 0; uint8_t val; - uint16_t status; char *busname; - uint32_t mcp_spibaraddr; - void *mcp_spibar; + uint32_t mcp6x_spibaraddr; struct pci_dev *smbusdev; msg_pinfo("This chipset is not really supported yet. Guesswork...\n"); @@ -1115,40 +1113,33 @@ smbusdev->bus, smbusdev->dev, smbusdev->func); /* Locate the BAR where the SPI interface lives. */ - mcp_spibaraddr = pci_read_long(smbusdev, 0x74); - msg_pdbg("SPI BAR is at 0x%08x, ", mcp_spibaraddr); + mcp6x_spibaraddr = pci_read_long(smbusdev, 0x74); + msg_pdbg("SPI BAR is at 0x%08x, ", mcp6x_spibaraddr); /* We hope this has native alignment. We know the SPI interface (well, * a set of GPIOs that is connected to SPI flash) is at offset 0x530, * so we expect a size of at least 0x800. Clear the lower bits. * It is entirely possible that the BAR is 64k big and the low bits are * reserved for an entirely different purpose. */ - mcp_spibaraddr &= ~0x7ff; - msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp_spibaraddr); + mcp6x_spibaraddr &= ~0x7ff; + msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp6x_spibaraddr); /* Accessing a NULL pointer BAR is evil. Don't do it. */ - if (mcp_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) { + if (mcp6x_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) { /* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */ - mcp_spibar = physmap("MCP67 SPI", mcp_spibaraddr, 0x544); + mcp6x_spibar = physmap("Nvidia MCP6x SPI", mcp6x_spibaraddr, 0x544); -/* Guessed. If this is correct, migrate to a separate MCP67 SPI driver. */ -#define MCP67_SPI_CS (1 << 1) -#define MCP67_SPI_SCK (1 << 2) -#define MCP67_SPI_MOSI (1 << 3) -#define MCP67_SPI_MISO (1 << 4) -#define MCP67_SPI_ENABLE (1 << 0) -#define MCP67_SPI_IDLE (1 << 8) - - status = mmio_readw(mcp_spibar + 0x530); - msg_pdbg("SPI control is 0x%04x, enable=%i, idle=%i\n", - status, status & 0x1, (status >> 8) & 0x1); + if (mcp6x_spi_init()) + ret = 1; +#if 0 /* FIXME: Remove the physunmap once the SPI driver exists. */ - physunmap(mcp_spibar, 0x544); - } else if (!mcp_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) { + physunmap(mcp6x_spibar, 0x544); +#endif + } else if (!mcp6x_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) { msg_pdbg("Strange. MCP SPI BAR is invalid.\n"); buses_supported &= ~CHIP_BUSTYPE_SPI; ret = 1; - } else if (mcp_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) { + } else if (mcp6x_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) { msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently" " doesn't have SPI enabled.\n"); } else { @@ -1186,8 +1177,7 @@ result = enable_flash_mcp55(dev, name); break; case CHIP_BUSTYPE_SPI: - msg_pinfo("SPI on this chipset is not supported yet.\n"); - buses_supported = CHIP_BUSTYPE_NONE; + msg_perr("SPI on this chipset is WIP. DO NOT USE!\n"); break; default: msg_pinfo("Something went wrong with bus type detection.\n"); @@ -1212,8 +1202,7 @@ msg_pinfo("LPC on this chipset is not supported yet.\n"); break; case CHIP_BUSTYPE_SPI: - msg_pinfo("SPI on this chipset is not supported yet.\n"); - buses_supported = CHIP_BUSTYPE_NONE; + msg_perr("SPI on this chipset is WIP. DO NOT USE!\n"); break; default: msg_pinfo("Something went wrong with bus type detection.\n"); only in patch2: unchanged: --- flashrom-bitbang_spi_nvidia_mcp/mcp6x_spi.c (Revision 0) +++ flashrom-bitbang_spi_nvidia_mcp/mcp6x_spi.c (Revision 0) @@ -0,0 +1,132 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Driver for the Nvidia MCP6x/MCP7x MCP6X_SPI controller. + * Based on clean room reverse engineered docs from + * http://www.flashrom.org/pipermail/flashrom/2009-December/001180.html + * created by Michael Karcher. + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include <stdint.h> +#include <stdlib.h> +#include <ctype.h> +#include "flash.h" + +/* We have two sets of pins, out and in. The numbers for both sets are + * independent and are bitshift values, not real pin numbers. + */ + +/* Guessed. */ +#define MCP6X_SPI_CS 1 +#define MCP6X_SPI_SCK 2 +#define MCP6X_SPI_MOSI 3 +#define MCP6X_SPI_MISO 4 +#define MCP6X_SPI_ENABLE 0 +#define MCP6X_SPI_IDLE 8 + +void *mcp6x_spibar = NULL; + +void mcp6x_request_spibus(void) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte |= 1 << MCP6X_SPI_ENABLE; + mmio_writeb(byte, mcp6x_spibar + 0x530); + + /* Wait until we are allowed to use the SPI bus. */ + while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_IDLE))) ; +} + +void mcp6x_release_spibus(void) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte &= ~(1 << MCP6X_SPI_ENABLE); + mmio_writeb(byte, mcp6x_spibar + 0x530); +} + +void mcp6x_bitbang_set_cs(int val) +{ + uint8_t byte; + + /* Requesting and releasing the SPI bus is handled in here to allow the + * chipset to use its own SPI engine for native reads. + */ + if (val == 1) + mcp6x_request_spibus(); + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte &= ~(1 << MCP6X_SPI_CS); + byte |= (val << MCP6X_SPI_CS); + mmio_writeb(byte, mcp6x_spibar + 0x530); + + if (val == 0) + mcp6x_release_spibus(); +} + +void mcp6x_bitbang_set_sck(int val) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte &= ~(1 << MCP6X_SPI_SCK); + byte |= (val << MCP6X_SPI_SCK); + mmio_writeb(byte, mcp6x_spibar + 0x530); +} + +void mcp6x_bitbang_set_mosi(int val) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte &= ~(1 << MCP6X_SPI_MOSI); + byte |= (val << MCP6X_SPI_MOSI); + mmio_writeb(byte, mcp6x_spibar + 0x530); +} + +int mcp6x_bitbang_get_miso(void) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte = (byte >> MCP6X_SPI_MISO) & 0x1; + return byte; +} + +int mcp6x_spi_init(void) +{ + uint16_t status; + + status = mmio_readw(mcp6x_spibar + 0x530); + msg_pdbg("SPI control is 0x%04x, enable=%i, idle=%i\n", + status, (status >> MCP6X_SPI_ENABLE) & 0x1, + (status >> MCP6X_SPI_IDLE) & 0x1); + + if (bitbang_spi_init()) + return 1; + spi_controller = SPI_CONTROLLER_MCP6X_BITBANG; + + return 0; +} + +#endif -- http://www.hailfinger.org/ _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
