On 27.05.2010 02:43, Carl-Daniel Hailfinger wrote: > Add Nvidia nForce MCP61/MCP65/MCP67/MCP78S/MCP73/MCP79 SPI flashing support. > > This code is totally untested and may fry your flash chip, explode > mysteriously and abduct your dog. > Do NOT try to read/write/erase with this code until we know that it > behaves correctly. > > Logs from "flashrom -V" on all newer Nvidia nForce chipsets appreciated. >
This patch includes the RayeR SPIPGM code as well because they depend on each other. Signed-off-by: Carl-Daniel Hailfinger <[email protected]> Index: flashrom-bitbang_spi_nvidia_mcp/flash.h =================================================================== --- flashrom-bitbang_spi_nvidia_mcp/flash.h (Revision 1048) +++ flashrom-bitbang_spi_nvidia_mcp/flash.h (Arbeitskopie) @@ -81,6 +81,9 @@ #if CONFIG_DEDIPROG == 1 PROGRAMMER_DEDIPROG, #endif +#if CONFIG_RAYER_BITBANG_SPI == 1 + PROGRAMMER_RAYER_BITBANG_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -128,13 +131,19 @@ void programmer_delay(int usecs); enum bitbang_spi_master { +#if CONFIG_RAYER_BITBANG_SPI == 1 + BITBANG_SPI_MASTER_RAYER, +#endif +#if CONFIG_INTERNAL == 1 +#if defined(__i386__) || defined(__x86_64__) + BITBANG_SPI_MASTER_MCP, +#endif +#endif BITBANG_SPI_INVALID /* This must always be the last entry. */ }; extern const int bitbang_spi_master_count; -extern enum bitbang_spi_master bitbang_spi_master; - struct bitbang_spi_master_entry { void (*set_cs) (int val); void (*set_sck) (int val); @@ -529,10 +538,31 @@ int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf); +/* rayer_bitbang_spi.c */ +#if CONFIG_RAYER_BITBANG_SPI == 1 +int rayer_bitbang_spi_init(void); +void rayer_bitbang_set_cs(int val); +void rayer_bitbang_set_sck(int val); +void rayer_bitbang_set_mosi(int val); +int rayer_bitbang_get_miso(void); +#endif + +/* mcp6x_spi.c */ +#if CONFIG_INTERNAL == 1 +#if defined(__i386__) || defined(__x86_64__) +extern void *mcp6x_spibar; +int mcp6x_spi_init(void); +void mcp6x_bitbang_set_cs(int val); +void mcp6x_bitbang_set_sck(int val); +void mcp6x_bitbang_set_mosi(int val); +int mcp6x_bitbang_get_miso(void); +#endif +#endif + /* bitbang_spi.c */ extern int bitbang_spi_half_period; extern const struct bitbang_spi_master_entry bitbang_spi_master_table[]; -int bitbang_spi_init(void); +int bitbang_spi_init(enum bitbang_spi_master master); int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf); @@ -635,6 +665,7 @@ SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, + SPI_CONTROLLER_MCP6X_BITBANG, #endif #endif #if CONFIG_FT2232_SPI == 1 @@ -649,6 +680,9 @@ #if CONFIG_DEDIPROG == 1 SPI_CONTROLLER_DEDIPROG, #endif +#if CONFIG_RAYER_BITBANG_SPI == 1 + SPI_CONTROLLER_RAYER_BITBANG, +#endif SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; Index: flashrom-bitbang_spi_nvidia_mcp/hwaccess.h =================================================================== --- flashrom-bitbang_spi_nvidia_mcp/hwaccess.h (Revision 1048) +++ flashrom-bitbang_spi_nvidia_mcp/hwaccess.h (Arbeitskopie) @@ -169,6 +169,10 @@ #define __DARWIN__ #endif +/* Clarification about OUTB/OUTW/OUTL argument order: + * OUT[BWL](val, port) + */ + #if defined(__FreeBSD__) || defined(__DragonFly__) #include <machine/cpufunc.h> #define off64_t off_t Index: flashrom-bitbang_spi_nvidia_mcp/bitbang_spi.c =================================================================== --- flashrom-bitbang_spi_nvidia_mcp/bitbang_spi.c (Revision 1048) +++ flashrom-bitbang_spi_nvidia_mcp/bitbang_spi.c (Arbeitskopie) @@ -32,11 +32,32 @@ enum bitbang_spi_master bitbang_spi_master = BITBANG_SPI_INVALID; const struct bitbang_spi_master_entry bitbang_spi_master_table[] = { - {}, /* This entry corresponds to BITBANG_SPI_INVALID. */ +#if CONFIG_RAYER_BITBANG_SPI == 1 + { + .set_cs = rayer_bitbang_set_cs, + .set_sck = rayer_bitbang_set_sck, + .set_mosi = rayer_bitbang_set_mosi, + .get_miso = rayer_bitbang_get_miso, + }, +#endif + +#if CONFIG_INTERNAL == 1 +#if defined(__i386__) || defined(__x86_64__) + { + .set_cs = mcp6x_bitbang_set_cs, + .set_sck = mcp6x_bitbang_set_sck, + .set_mosi = mcp6x_bitbang_set_mosi, + .get_miso = mcp6x_bitbang_get_miso, + }, +#endif +#endif + + {}, /* This entry corresponds to SPI_BITBANG_INVALID. */ }; const int bitbang_spi_master_count = ARRAY_SIZE(bitbang_spi_master_table); +/* Note that CS# is active low, so val=0 means the chip is active. */ void bitbang_spi_set_cs(int val) { bitbang_spi_master_table[bitbang_spi_master].set_cs(val); @@ -57,10 +78,18 @@ return bitbang_spi_master_table[bitbang_spi_master].get_miso(); } -int bitbang_spi_init(void) +int bitbang_spi_init(enum bitbang_spi_master master) { + bitbang_spi_master = master; + + if (bitbang_spi_master == BITBANG_SPI_INVALID) { + msg_perr("Invalid bitbang SPI master. \n" + "Please report a bug at [email protected]\n"); + return 1; + } bitbang_spi_set_cs(1); bitbang_spi_set_sck(0); + bitbang_spi_set_mosi(0); buses_supported = CHIP_BUSTYPE_SPI; return 0; } @@ -87,6 +116,7 @@ { static unsigned char *bufout = NULL; static unsigned char *bufin = NULL; + unsigned char *tmp; static int oldbufsize = 0; int bufsize; int i; @@ -98,20 +128,34 @@ bufsize = max(writecnt + readcnt, 260); /* Never shrink. realloc() calls are expensive. */ if (bufsize > oldbufsize) { - bufout = realloc(bufout, bufsize); - if (!bufout) { + tmp = realloc(bufout, bufsize); + if (!tmp) { msg_perr("Out of memory!\n"); + if (bufout) + free(bufout); + bufout = NULL; if (bufin) free(bufin); + bufin = NULL; + oldbufsize = 0; exit(1); - } - bufin = realloc(bufout, bufsize); - if (!bufin) { + } else + bufout = tmp; + + tmp = realloc(bufin, bufsize); + if (!tmp) { msg_perr("Out of memory!\n"); + if (bufin) + free(bufin); + bufin = NULL; if (bufout) free(bufout); + bufout = NULL; + oldbufsize = 0; exit(1); - } + } else + bufin = tmp; + oldbufsize = bufsize; } @@ -135,8 +179,13 @@ int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { - /* Maximum read length is unlimited, use 64k bytes. */ - return spi_read_chunked(flash, buf, start, len, 64 * 1024); + /* Maximum read length is unlimited in theory. + * The current implementation can handle reads of up to 65536 bytes. + * Please note that you need two buffers of 2n+4 bytes each for a read + * of n bytes, resulting in a total memory requirement of 4n+8 bytes. + * To conserve memory, read in chunks of 256 bytes. + */ + return spi_read_chunked(flash, buf, start, len, 256); } int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf) Index: flashrom-bitbang_spi_nvidia_mcp/Makefile =================================================================== --- flashrom-bitbang_spi_nvidia_mcp/Makefile (Revision 1048) +++ flashrom-bitbang_spi_nvidia_mcp/Makefile (Arbeitskopie) @@ -107,8 +107,19 @@ # Always enable serprog for now. Needs to be disabled on Windows. CONFIG_SERPROG ?= yes -# Bitbanging SPI infrastructure is not used yet. +# RayeR SPIPGM hardware support +CONFIG_RAYER_BITBANG_SPI ?= yes + +# Bitbanging SPI infrastructure, default off unless needed. +ifeq ($(CONFIG_RAYER_BITBANG_SPI), yes) +CONFIG_BITBANG_SPI = yes +else +ifeq ($(CONFIG_INTERNAL), yes) +CONFIG_BITBANG_SPI = yes +else CONFIG_BITBANG_SPI ?= no +endif +endif # Always enable 3Com NICs for now. CONFIG_NIC3COM ?= yes @@ -151,7 +162,7 @@ FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o # FIXME: The PROGRAMMER_OBJS below should only be included on x86. -PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o +PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o NEED_PCI := yes endif @@ -162,6 +173,13 @@ NEED_NET := yes endif +ifeq ($(CONFIG_RAYER_BITBANG_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_RAYER_BITBANG_SPI=1' +PROGRAMMER_OBJS += rayer_bitbang_spi.o +# Actually, NEED_PCI is wrong. NEED_IOPORT_ACCESS would be more correct. +NEED_PCI := yes +endif + ifeq ($(CONFIG_BITBANG_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_BITBANG_SPI=1' PROGRAMMER_OBJS += bitbang_spi.o Index: flashrom-bitbang_spi_nvidia_mcp/spi25.c =================================================================== --- flashrom-bitbang_spi_nvidia_mcp/spi25.c (Revision 1048) +++ flashrom-bitbang_spi_nvidia_mcp/spi25.c (Arbeitskopie) @@ -178,6 +178,7 @@ case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: + case SPI_CONTROLLER_MCP6X_BITBANG: #endif #endif #if CONFIG_FT2232_SPI == 1 @@ -192,6 +193,9 @@ #if CONFIG_DEDIPROG == 1 case SPI_CONTROLLER_DEDIPROG: #endif +#if CONFIG_RAYER_BITBANG_SPI == 1 + case SPI_CONTROLLER_RAYER_BITBANG: +#endif return probe_spi_rdid_generic(flash, 4); default: msg_cinfo("4b ID not supported on this SPI controller\n"); Index: flashrom-bitbang_spi_nvidia_mcp/spi.c =================================================================== --- flashrom-bitbang_spi_nvidia_mcp/spi.c (Revision 1048) +++ flashrom-bitbang_spi_nvidia_mcp/spi.c (Arbeitskopie) @@ -83,6 +83,13 @@ .read = wbsio_spi_read, .write_256 = wbsio_spi_write_1, }, + + { /* SPI_CONTROLLER_MCP6X_BITBANG */ + .command = bitbang_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = bitbang_spi_read, + .write_256 = bitbang_spi_write_256, + }, #endif #endif @@ -122,6 +129,15 @@ }, #endif +#if CONFIG_RAYER_BITBANG_SPI == 1 + { /* SPI_CONTROLLER_RAYER_BITBANG */ + .command = bitbang_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = bitbang_spi_read, + .write_256 = bitbang_spi_write_256, + }, +#endif + {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ }; Index: flashrom-bitbang_spi_nvidia_mcp/chipset_enable.c =================================================================== --- flashrom-bitbang_spi_nvidia_mcp/chipset_enable.c (Revision 1048) +++ flashrom-bitbang_spi_nvidia_mcp/chipset_enable.c (Arbeitskopie) @@ -1092,10 +1092,8 @@ { int ret = 0; uint8_t val; - uint16_t status; char *busname; - uint32_t mcp_spibaraddr; - void *mcp_spibar; + uint32_t mcp6x_spibaraddr; struct pci_dev *smbusdev; msg_pinfo("This chipset is not really supported yet. Guesswork...\n"); @@ -1144,40 +1142,33 @@ smbusdev->bus, smbusdev->dev, smbusdev->func); /* Locate the BAR where the SPI interface lives. */ - mcp_spibaraddr = pci_read_long(smbusdev, 0x74); - msg_pdbg("SPI BAR is at 0x%08x, ", mcp_spibaraddr); + mcp6x_spibaraddr = pci_read_long(smbusdev, 0x74); + msg_pdbg("SPI BAR is at 0x%08x, ", mcp6x_spibaraddr); /* We hope this has native alignment. We know the SPI interface (well, * a set of GPIOs that is connected to SPI flash) is at offset 0x530, * so we expect a size of at least 0x800. Clear the lower bits. * It is entirely possible that the BAR is 64k big and the low bits are * reserved for an entirely different purpose. */ - mcp_spibaraddr &= ~0x7ff; - msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp_spibaraddr); + mcp6x_spibaraddr &= ~0x7ff; + msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp6x_spibaraddr); /* Accessing a NULL pointer BAR is evil. Don't do it. */ - if (mcp_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) { + if (mcp6x_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) { /* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */ - mcp_spibar = physmap("MCP67 SPI", mcp_spibaraddr, 0x544); + mcp6x_spibar = physmap("Nvidia MCP6x SPI", mcp6x_spibaraddr, 0x544); -/* Guessed. If this is correct, migrate to a separate MCP67 SPI driver. */ -#define MCP67_SPI_CS (1 << 1) -#define MCP67_SPI_SCK (1 << 2) -#define MCP67_SPI_MOSI (1 << 3) -#define MCP67_SPI_MISO (1 << 4) -#define MCP67_SPI_ENABLE (1 << 0) -#define MCP67_SPI_IDLE (1 << 8) - - status = mmio_readw(mcp_spibar + 0x530); - msg_pdbg("SPI control is 0x%04x, enable=%i, idle=%i\n", - status, status & 0x1, (status >> 8) & 0x1); + if (mcp6x_spi_init()) + ret = 1; +#if 0 /* FIXME: Remove the physunmap once the SPI driver exists. */ - physunmap(mcp_spibar, 0x544); - } else if (!mcp_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) { + physunmap(mcp6x_spibar, 0x544); +#endif + } else if (!mcp6x_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) { msg_pdbg("Strange. MCP SPI BAR is invalid.\n"); buses_supported &= ~CHIP_BUSTYPE_SPI; ret = 1; - } else if (mcp_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) { + } else if (mcp6x_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) { msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently" " doesn't have SPI enabled.\n"); } else { @@ -1215,8 +1206,7 @@ result = enable_flash_mcp55(dev, name); break; case CHIP_BUSTYPE_SPI: - msg_pinfo("SPI on this chipset is not supported yet.\n"); - buses_supported = CHIP_BUSTYPE_NONE; + msg_perr("SPI on this chipset is WIP. DO NOT USE!\n"); break; default: msg_pinfo("Something went wrong with bus type detection.\n"); @@ -1241,8 +1231,7 @@ msg_pinfo("LPC on this chipset is not supported yet.\n"); break; case CHIP_BUSTYPE_SPI: - msg_pinfo("SPI on this chipset is not supported yet.\n"); - buses_supported = CHIP_BUSTYPE_NONE; + msg_perr("SPI on this chipset is WIP. DO NOT USE!\n"); break; default: msg_pinfo("Something went wrong with bus type detection.\n"); Index: flashrom-bitbang_spi_nvidia_mcp/mcp6x_spi.c =================================================================== --- flashrom-bitbang_spi_nvidia_mcp/mcp6x_spi.c (Revision 0) +++ flashrom-bitbang_spi_nvidia_mcp/mcp6x_spi.c (Revision 0) @@ -0,0 +1,132 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Driver for the Nvidia MCP6x/MCP7x MCP6X_SPI controller. + * Based on clean room reverse engineered docs from + * http://www.flashrom.org/pipermail/flashrom/2009-December/001180.html + * created by Michael Karcher. + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include <stdint.h> +#include <stdlib.h> +#include <ctype.h> +#include "flash.h" + +/* We have two sets of pins, out and in. The numbers for both sets are + * independent and are bitshift values, not real pin numbers. + */ + +/* Guessed. */ +#define MCP6X_SPI_CS 1 +#define MCP6X_SPI_SCK 2 +#define MCP6X_SPI_MOSI 3 +#define MCP6X_SPI_MISO 4 +#define MCP6X_SPI_ENABLE 0 +#define MCP6X_SPI_IDLE 8 + +void *mcp6x_spibar = NULL; + +void mcp6x_request_spibus(void) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte |= 1 << MCP6X_SPI_ENABLE; + mmio_writeb(byte, mcp6x_spibar + 0x530); + + /* Wait until we are allowed to use the SPI bus. */ + while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_IDLE))) ; +} + +void mcp6x_release_spibus(void) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte &= ~(1 << MCP6X_SPI_ENABLE); + mmio_writeb(byte, mcp6x_spibar + 0x530); +} + +void mcp6x_bitbang_set_cs(int val) +{ + uint8_t byte; + + /* Requesting and releasing the SPI bus is handled in here to allow the + * chipset to use its own SPI engine for native reads. + */ + if (val == 1) + mcp6x_request_spibus(); + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte &= ~(1 << MCP6X_SPI_CS); + byte |= (val << MCP6X_SPI_CS); + mmio_writeb(byte, mcp6x_spibar + 0x530); + + if (val == 0) + mcp6x_release_spibus(); +} + +void mcp6x_bitbang_set_sck(int val) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte &= ~(1 << MCP6X_SPI_SCK); + byte |= (val << MCP6X_SPI_SCK); + mmio_writeb(byte, mcp6x_spibar + 0x530); +} + +void mcp6x_bitbang_set_mosi(int val) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte &= ~(1 << MCP6X_SPI_MOSI); + byte |= (val << MCP6X_SPI_MOSI); + mmio_writeb(byte, mcp6x_spibar + 0x530); +} + +int mcp6x_bitbang_get_miso(void) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte = (byte >> MCP6X_SPI_MISO) & 0x1; + return byte; +} + +int mcp6x_spi_init(void) +{ + uint16_t status; + + status = mmio_readw(mcp6x_spibar + 0x530); + msg_pdbg("SPI control is 0x%04x, enable=%i, idle=%i\n", + status, (status >> MCP6X_SPI_ENABLE) & 0x1, + (status >> MCP6X_SPI_IDLE) & 0x1); + + if (bitbang_spi_init(BITBANG_SPI_MASTER_MCP)) + return 1; + spi_controller = SPI_CONTROLLER_MCP6X_BITBANG; + + return 0; +} + +#endif Index: flashrom-bitbang_spi_nvidia_mcp/flashrom.c =================================================================== --- flashrom-bitbang_spi_nvidia_mcp/flashrom.c (Revision 1048) +++ flashrom-bitbang_spi_nvidia_mcp/flashrom.c (Arbeitskopie) @@ -48,7 +48,7 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG > 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_BITBANG_SPI > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. #endif enum programmer programmer = @@ -86,6 +86,9 @@ #if CONFIG_DEDIPROG == 1 PROGRAMMER_DEDIPROG #endif +#if CONFIG_RAYER_BITBANG_SPI == 1 + PROGRAMMER_RAYER_BITBANG_SPI +#endif ; #endif @@ -394,6 +397,25 @@ }, #endif +#if CONFIG_RAYER_BITBANG_SPI == 1 + { + .name = "rayer_bitbang_spi", + .init = rayer_bitbang_spi_init, + .shutdown = noop_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = noop_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = noop_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + {}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; Index: flashrom-bitbang_spi_nvidia_mcp/rayer_bitbang_spi.c =================================================================== --- flashrom-bitbang_spi_nvidia_mcp/rayer_bitbang_spi.c (Revision 0) +++ flashrom-bitbang_spi_nvidia_mcp/rayer_bitbang_spi.c (Revision 0) @@ -0,0 +1,112 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009,2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Driver for the SPIPGM hardware by "RayeR" Martin Rehak. + * See http://rayer.ic.cz/elektro/spipgm.htm for schematics and instructions. + */ + +/* This driver uses non-portable direct I/O port accesses which won't work on + * any non-x86 platform, and even on x86 there is a high chance there will be + * collisions with any loaded parallel port drivers. + * The big advantage of direct port I/O is OS independence and speed because + * most OS parport drivers will perform many unnecessary accesses although + * this driver just treats the parallel port as a GPIO set. + */ +#if defined(__i386__) || defined(__x86_64__) + +#include "flash.h" + +/* We have two sets of pins, out and in. The numbers for both sets are + * independent and are bitshift values, not real pin numbers. + */ +/* Pins for master->slave direction */ +#define SPI_CS_PIN 5 +#define SPI_SCK_PIN 6 +#define SPI_MOSI_PIN 7 +/* Pins for slave->master direction */ +#define SPI_MISO_PIN 6 + +static int lpt_iobase; + +/* FIXME: All rayer_bitbang_set_* functions could use caching of the value + * stored at port lpt_iobase to avoid unnecessary INB. In theory, only one + * INB(lpt_iobase) would be needed on programmer init to get the initial + * value. + */ + +void rayer_bitbang_set_cs(int val) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase); + tmp &= ~(1 << SPI_CS_PIN); + tmp |= (val << SPI_CS_PIN); + OUTB(tmp, lpt_iobase); +} + +void rayer_bitbang_set_sck(int val) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase); + tmp &= ~(1 << SPI_SCK_PIN); + tmp |= (val << SPI_SCK_PIN); + OUTB(tmp, lpt_iobase); +} + +void rayer_bitbang_set_mosi(int val) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase); + tmp &= ~(1 << SPI_MOSI_PIN); + tmp |= (val << SPI_MOSI_PIN); + OUTB(tmp, lpt_iobase); +} + +int rayer_bitbang_get_miso(void) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase + 1); + tmp = (tmp >> SPI_MISO_PIN) & 0x1; + return tmp; +} + +int rayer_bitbang_spi_init(void) +{ + /* Pick a default value for now. */ + lpt_iobase = 0x378; + + msg_pdbg("Using port 0x%x as I/O base for parallel port access.\n", + lpt_iobase); + + get_io_perms(); + + if (bitbang_spi_init(BITBANG_SPI_MASTER_RAYER)) + return 1; + + spi_controller = SPI_CONTROLLER_RAYER_BITBANG; + + return 0; +} + +#else +#error PCI port I/O access is not supported on this architecture yet. +#endif -- http://www.hailfinger.org/ _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
