Hi Daniel, On 17.06.2010 18:01, Daniel Flinkmann wrote: > I have some news: > > Am 17.06.2010 um 12:32 schrieb Carl-Daniel Hailfinger: > >>> At the moment I am still waiting for the end of the write flash command, >>> which is running since 23:22 CET yesterday (So that are 8 hour running). >>> >>> >> If I take into account the too long timing you were experiencing during >> read, the expected write time (with my 3x speedup patch) is roughly 9 hours. >> > > Finally I know that it was running from 07:40:08 to 16:57:18 , so 9hrs 17min > 10secs . So your calculation was > perfect. (See below) >
Glad to hear my estimates were correct. This also means that something is slowing down all accesses with the same factor (not good). >>> Erasing was complete at aprox 23:38:30 , so roughly after 13 minutes, which >>> is much better. Up to now, I am waiting 8 hours to see any additional >>> reporting, but flashrom is still running. >>> >>> >> It might make sense to abort if it is still running after 12 hours total >> (4 hours after your mail). If you abort, please read the chip afterwards >> and upload the read file here: http://wedgewww.dyndns.org/uploader/ >> > > The following log is the whole erase/write run with the 1048 + > 3x-speed-bp-patch . > > I am currently making a second read test to see if the flashed binary is > still correct. > > Thu Jun 17 07:40:08 CEST 2010 > flashrom v0.9.2-r1048-with-3xspeed-bp-patch on Linux 2.6.32-22-server > (x86_64), built with libpci 3.0.0, GCC 4.4.3, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 299M loops per > second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 998 us, 10000 myus = > 10013 us, 4 myus = 5 us, OK. > Initializing buspirate_spi programmer > SPI speed is 8MHz > Raw bitbang mode version 1 > Raw SPI mode version 1 > Probing for Atmel AT25DF021, 256 KB: RDID byte 0 parity violation. > probe_spi_rdid_generic: id1 0x00, id2 0x00 > Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 > 0x258e > Chip status register is 1c > Chip status register: Block Protect Write Disable (BPL) is not set > Chip status register: Auto Address Increment Programming (AAI) is not set > Chip status register: Bit 5 / Block Protect 3 (BP3) is not set > Chip status register: Bit 4 / Block Protect 2 (BP2) is set > Chip status register: Bit 3 / Block Protect 1 (BP1) is set > Chip status register: Bit 2 / Block Protect 0 (BP0) is set > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > Found chip "SST SST25VF080B" (1024 KB, SPI) at physical address 0xfff00000. > Flash image seems to be a legacy BIOS. Disabling checks. > Writing flash chip... Some block protection in effect, disabling > Erasing flash before programming... Erasing flash chip... Looking at > blockwise erase function 0... trying... 0x000000-0x000fff, 0x001000-0x001fff, > 0x002000-0x002fff, 0x003000-0x003fff, 0x004000-0x004fff, 0x005000-0x005fff, > 0x006000-0x006fff, 0x007000-0x007fff, 0x008000-0x008fff, 0x009000-0x009fff, > 0x00a000-0x00afff, 0x00b000-0x00bfff, 0x00c000-0x00cfff, 0x00d000-0x00dfff, > 0x00e000-0x00efff, 0x00f000-0x00ffff, 0x010000-0x010fff, 0x011000-0x011fff, > 0x012000-0x012fff, 0x013000-0x013fff, 0x014000-0x014fff, 0x015000-0x015fff, > 0x016000-0x016fff, 0x017000-0x017fff, 0x018000-0x018fff, 0x019000-0x019fff, > 0x01a000-0x01afff, 0x01b000-0x01bfff, 0x01c000-0x01cfff, 0x01d000-0x01dfff, > 0x01e000-0x01efff, 0x01f000-0x01ffff, 0x020000-0x020fff, 0x021000-0x021fff, > 0x022000-0x022fff, 0x023000-0x023fff, 0x024000-0x024fff, 0x025000-0x025fff, > 0x026000-0x026fff, 0x027000-0x027fff, 0x028000-0x028fff, 0x029000-0x029fff, > 0x02a000-0x02afff, 0x02b000-0x02bfff, 0x02c000-0x02cfff, 0x02d000-0x02dfff, > 0x02e000-0x02efff, 0x02f000-0x02ffff, 0x0 > SUCCESS. > done. > COMPLETE. > Verifying flash... VERIFIED. > Raw bitbang mode version 1 > Bus Pirate shutdown completed. > Thu Jun 17 16:57:18 CEST 2010 > Congratulations! > Just a general thing when I have a look at the flash process output: > > 1. Writing flash chip... > 2. Erasing flash before programming... > 3. SUCCESS. > 4. done. > 5. COMPLETE. > 6. Verifying flash... > 7. VERIFIED. > > So for me as a (happy bunny) user I can be sure that flashrom is: > (1) starting to write the flash chip, > (2) starting to erase the flash before programming, > (3) sucessfully done something > (4) done again something, > (5) Completed something, > (6) starting to verify > (7) sucessfully verified the flash write. > > It is a bit inconsistent in the user interface. > Yes. This is caused by activating the verbose switch. The normal output is a lot more readable AFAIK. > I would be happy to see the output similar to this: > > Writing flash chip... > Erasing flash before programming... > ERASED > Programming flash ... > PROGRAMMED > Starting to verify ... > VERIFIED > > > > When I used flashrom the first time, I was pretty much confused by the > "done." at the end and I wasn't sure that flashrom is now programming > the flash. I assumed it would have completed its work, but don't exit > the application. It could be that I am not the only one who suddenly > fall into this trap ;-) > I know it's just nitpicking, but sometimes these views from the 3rd > person helps. Yes, thanks. We should probably change the messages a bit. However, it seems progress printing is also very important and maybe it should even come first. > I have also done a second read test to ensure that the flash was > really successfully written. > Again the time to read the flash was just 15 min 7sec and both > Original and re-read flash binary > were exactly the same: > # md5sum JX58D422.BIN readtest-after-flash.bin > 52c44f00eecaad3626c3d8b42f1dd1d8 JX58D422.BIN > 52c44f00eecaad3626c3d8b42f1dd1d8 readtest-after-flash.bin Very nice. > Log: > Thu Jun 17 17:35:18 CEST 2010 > flashrom v0.9.2-r1048-with-3xspeed-bp-patch on Linux 2.6.32-22-server > (x86_64), built with libpci 3.0.0, GCC 4.4.3, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found chip "SST SST25VF080B" (1024 KB, SPI) at physical address > 0xfff00000. > Reading flash... done. > Thu Jun 17 17:50:25 CEST 2010 Excellent. > Please let me know if I can do any additional tests for you. Could you run "flashrom -VV" with a completely unpatched flashrom? I'd like to give Ian Lesnet (Bus Pirate creator) a full log which he requested here: http://dangerousprototypes.com/forum/index.php?topic=651.0 Thanks again for all the testing you did. Kind regards, Carl-Daniel -- http://www.hailfinger.org/ _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
