>> Adrian correctly pointed out that tagging is a time/space trade-off. I did >> demonstrate that different processors did perform differently by varying >> tagging schemes. > > Yes, the current tagging scheme (with 0 as nil) seemed to perform best > in your benchmark. But will it make a difference for more typical usage > (such as idc compiling itself)? > >> There is an interest in porting FoNC to smaller and larger >> architectures. If tagging schemes have limited benefit then why decide on >> any >> tagging scheme? There are valid reasons modern systems do not use high-bit >> tags; I propose there are valid reasons to not hard-code a particular tagging >> scheme into a flexible system like FoNC.
I'm new to this list, so pardon me if this is off-topic. I'm working on a prototype micro-kernel (in C) that currently runs on x86 but is ultimately targeted to run on an ARM processor as well. On the ARM, it is possible to include a shift into any data access opcode without incurring additional execution cycles. This creates a different set of interesting trade-offs WRT performant type tagging. I've experimented with a couple of different tagging schemes, some intended to leave bits available for marking by the garbage collector. I've isolated all the tagging policies into a small set of macros. This allowed me to switch from using 3-MSB to 2-LSB without changing anything except the macro definitions. The meta-question I have is: Is this an appropriate place to discuss micro-kernel design issues in general, or is it VPRI/COLA specific? It seems to me that we have a lot in common. I have certainly enjoyed learning from your published experiences. _______________________________________________ fonc mailing list fonc@vpri.org http://vpri.org/mailman/listinfo/fonc
