Could you clarify what you're thinking about? Is your question about metaprogramming of Verilog (with an implicit assumption that Verilog will save battery life)?
I've spent much time thinking about language and protocol design to extend battery resources. I happen to think the real wins are at higher levels - avoiding unnecessary work, amortizing work over time, linear logics, graceful degradation of services based on power access. (Questions about power and energy were common in survivable networking courses.) Low level power saving is a common aspect of mobile computer architecture design. But it's hard to push fundamentally better hardware designs without an existing body of software that easily fits it. On Nov 30, 2012 2:06 PM, "Casey Ransberger" <[email protected]> wrote: > Since I'm running out of battery, and my adder is starting to go oh so > slowly, I thought I might challenge the lovely people of the list to make > it stop draining my battery so quickly. > > :D > > My first challenge idea was for someone to make it stop raining in > Seattle, but I realized that I was asking a lot with that. > > Verilog would be cool, but better if you're translating whatcha got to > Verilog with OMeta, and you've come up with some randomly pretty language > for wires! > > Come on, someone else has to be thinking about this;) > > -- > Casey Ransberger > > _______________________________________________ > fonc mailing list > [email protected] > http://vpri.org/mailman/listinfo/fonc > >
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