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> > Anyone clueful want to nominate > > an xA1 IdentifyPacketDevice bit to fix this: > > to make SwDma/MwDma/UDma > > as capable of precise byte counts as Pio? > > > > If the bit is set, > > then the device promises, > > in the x03 StatusIn phase > > after some Dma data moved out, > > to set x1F5:1F4 to the bytes > > it received but did not request. > Wouldn't it make more sense ... > to just require valid byte counts > from the drive before each DMA burst, > just like in PIO? Very much more like we're used to thinking about Pio, yes ... but does it work? I think maybe we should change not how Pio works but how we think about how Pio works. Rather than saying the host moves the count D of bytes that the device requests, we can say the host clocks ((1 + D) / 2) pairs of bytes across the bus and but decides whether or not to toss/pad the last byte. > to just require valid byte counts > from the drive before each DMA burst, Would that somehow be more informative? Maybe more than minimally informative? I'm thinking that's a much larger change to protocol. I'm told, dunno if I believe, that our shipping legacy actually does this already: stuff the count of each Dma burst into the task file. But making sense of that number in the context of how indeterminately UDma pauses could be pretty tough? In any case, to see those numbers, a host would have to depart far from the design rule of TalkLikeWindows. The host would have to terminate Dma much more often, deassert DMACK-, poll the task file ... all with no encouragement by INTRQ as in PIO ... doesn't seem likely? > That's the only way > to make DMA and PIO "bug-for-bug compatible". Please say more, I don't follow. Thanks for talking. Pat LaVarre Subscribe/Unsubscribe instructions can be found at www.t13.org.
