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Jim,

In ATA-6 r 3, section 7.6.4 (Effect of the Data Register), it states that: 

"PIO data-out transfers are processed by a series of reads to this register,
each read transferring the data that
follows the previous read. PIO data-in transfers are processed by a series
of writes to this register, each write
transferring the data that follows the previous write. The results of a read
during a PIO in or a write during a PIO
out are indeterminate."

So the case is covered, although documented incorrectly (note: the sense of
DATA-IN and DATA-OUT are reversed in the above text, so that should be
corrected).

Jim


-----Original Message-----
From: Jim Castleberry [mailto:[EMAIL PROTECTED]]
Sent: Thursday, December 06, 2001 8:56 AM
To: Pat LaVarre
Cc: [EMAIL PROTECTED]
Subject: Re: [t13] a fix for imprecise UDma residue?


This message is from the T13 list server.


On Tue, Dec 04, 2001 at 12:42:52PM -0700, Pat LaVarre wrote:
> Anyone clueful want to nominate an xA1 IdentifyPacketDevice bit to fix
this: to make SwDma/MwDma/UDma as capable of precise byte counts as Pio?
> 
> If the bit is set, then the device promises, in the x03 StatusIn phase
after some Dma data moved out, to set x1F5:1F4 to the bytes it received but
did not request.

Wouldn't it make more sense to just require valid byte counts from the
drive before each DMA burst, just like in PIO?  That's the only way to
make DMA and PIO "bug-for-bug compatible".  (Getting host controllers
to use either mechanism is another matter.)

Related question: what shall an ATAPI device do if the host doesn't
restrict itself to the given byte count and reads or writes the data
register too many times in PIO?  Or for that matter what shall an ATA
or ATAPI device if the host reads data when the devices expects writes
or vice versa?  The one time I saw this in the lab (due to an
application defect) the drive completely ignored the data and sat there
with DRQ set forever.  The smart thing would be to terminate the command
and report an error (which one?).  But I don't think the ATA spec says,
does it?

jcastle

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