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ATA/ATAPI-6 has two tables for PIO timing, one called "Register transfer timing to/from device" and the other called "PIO data transfer to/from/device". They're identical except for t2, nDIOx pulse width, which is 290 ns for modes 0-2 in the Register table and 165, 125, and 100 ns in the data table. I've interpreted that to mean that the host could only use the shorter pulse widths for the data register and had to use 290 ns for all the other registers. But a co-worker just pointed out to me that ATA-3 has only one PIO timing table, and it shows the faster numbers. ATA-2 has only one table but it contains two sets of numbers for t2 - one row labeled "(16 bit)" and the other labeled "(8 bit)". Looking at the history from ATA-2 to ATA-3 it seems like the long timings might have been for 8-bit mode, where the data register is 8 bits too, and when 8-bit mode was obsoleted in ATA-3 the long timings went away. I haven't looked at ATA-4 or ATA-5 to see what they show. The text that goes with the timing is virtually unchanged since ATA-2 and it's no help at all. So... what does the Register table apply to - all registers other than data, all registers only when the disk is set to 8-bit mode, something else? And why did the long t2 disappear in ATA-3 and then come back? Could ATA-3 actually permit faster timing than later specs? jcastle Subscribe/Unsubscribe instructions can be found at www.t13.org.
