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Again I forgot to copy the reflector... ==================BEGIN FORWARDED MESSAGE================== >To: "Jim Castleberry" <[EMAIL PROTECTED]> >Date: Thu, 06 Dec 2001 17:42:24 -0700 >From: "Hale Landis" <[EMAIL PROTECTED]> >Subject: Re: [t13] Register vs. data PIO timing On Thu, 6 Dec 2001 17:04:52 -0700 (MST), Jim Castleberry wrote: >ATA/ATAPI-6 has two tables for PIO timing, one called "Register >transfer timing to/from device" and the other called "PIO data >transfer to/from/device". They're identical except for t2, nDIOx >pulse width, which is 290 ns for modes 0-2 in the Register table >and 165, 125, and 100 ns in the data table. Yes... The PIO timing tables have been this way since ATA-3 and as far as I can tell not much has changed in those tables since ATA-1 or ATA-2. The original single table was split into two tables in hopes that it would make it more clear that the timings for the Data register are different than for the other Command and Control Block registers. This has nothing to do with 8-bit data transfers. The timings for 8-bit data transfers were never specified by ATA-x. It was only when 8-bit transfers were put back into ATA/ATAPI-x was it made clear that the PIO timings for the Data register apply to both 16-bit and 8-bit transfers (for devices that support 8-bit data transfers). >I've interpreted that to mean that the host could only use the >shorter pulse widths for the data register and had to use 290 ns >for all the other registers. This is correct. >But a co-worker just pointed out to >me that ATA-3 has only one PIO timing table, and it shows the >faster numbers. My copy of ATA-3 (rev 7b) has two PIO timing tables. >So... what does the Register table apply to - all registers other >than data, all registers only when the disk is set to 8-bit mode, >something else? The PIO Register Transfer table applies to all of the Command and Control Block registers not including the Data register. The PIO Data Transfer table applies to the Data register for both 16-bit and 8-bit modes of PIO data transfer. Of course the Data register should not be accessed unless BSY=0 and DRQ=1 during a command that transfers data in PIO mode (I say that because some devices have BSY=0 DRQ=1 during R/W DMA commands when the Data register is really the Data port). >And why did the long t2 disappear in ATA-3 and then come back? >Could ATA-3 actually permit faster timing than later specs? Could you have something other than the final draft of ATA-3? ===================END FORWARDED MESSAGE=================== *** Hale Landis *** [EMAIL PROTECTED] *** *** Niwot, CO USA *** www.ata-atapi.com *** Subscribe/Unsubscribe instructions can be found at www.t13.org.
