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Thanks for responding, Mike! Of course I knew that this is how Intel controllers have worked for ages.... But this says NOTHING about what the DEVICE manufacturers did to get this stuff to work (via IGNORING that blasted table) in developing their hardware! In other words, having a few million Intel controllers out there working says NOTHING about the target devices. (to make my point, I have never seen an Intel Data Path Controller...) So, we make all accesses to 1F1-1F7 work at PIO-0, and 1F0 is PIO-4 via an Intel controller. How do you know that the devices (that successfully work) aren't ALWAYS set up to handle selection (and write pulses, as Pat pointed out) at PIO-4 anyways? After all, 1F1-1F7 registers are usually in the DPC, and are BOUND to be a heck of a lot faster than the buffer access port 1F0 anyway, which usually feeds a FIFO, and additionally must arbitrate for the buffer. It's still my opinion: the table is really actually never used, except for the cycle times! After all, as far as the 1F1-1F7 logic is concerned (per my example), the select/write pulses STILL look like noise IF THEY ARE ACTUALLY IMPLEMENTED USING SLOW LOGIC. The address lines being stable only helps AFTER 'n' pulses ... those 'n' accumulating to the PIO-0 timing for the setup time required by the slow logic. I don't see the table accounting for this "phantom" first needed access setup (nor last access hold) time. Besides, how do you predict the effects of unruly short write pulses [from the perspective of the slow hardware], anyhow? Like I said in my last email, Mike, "I'd sure like to see actual hardware that could RELIABLY handle all sorts of varying select times beyond their ******DESIGNED***** limits". Device manufacturers always designing for mode 4/3/2 because the table doesn't make sense, does not validate your argument that millions of Intel controllers work...it only says that mode 4/3/2 devices always work at mode 0 on 1F1-1F7. My example (highly unrealistic, and extreme) was meant to show how inhospitable the table was to a stable hardware environment, and one that would have "standard" hardware designers yelling "eeeeeeeek!" and running for the exits :) (In my opinion, of course) =-ron At 08:25 AM 12/10/2001, you wrote: >This message is from the T13 list server. > > >Well Ron I hate to tell you, but all Intel ATA controllers have worked like >this for years. Long before I came along, someone chose to allow PIO-0 for >1f1-1f7, and PIO-4 for 1f0. The characteristic that makes it all work is >the chipset never changes the address lines when transferring data, so you >can have different timings on the two different logic chains and it all >works (for at least a few hundred million users out there). Phantom >hardware? I think not. > >We can argue this one out tommorrow at the T13 meeting. See you there. Subscribe/Unsubscribe instructions can be found at www.t13.org.
