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I sent this to Pat but not to the reflector a few hours ago... ==================BEGIN FORWARDED MESSAGE================== >To: "Pat LaVarre" <[EMAIL PROTECTED]> >Date: Thu, 06 Dec 2001 12:45:57 -0700 >From: "Hale Landis" <[EMAIL PROTECTED]> >Subject: Re: [t13] Re: unexpected data clocks On Thu, 06 Dec 2001 10:54:58 -0700, Pat LaVarre wrote: >For Pio I guess I think of this as a special case of >how to respond to Pio r/w of the x1F0 Data register >at times when DRQ is clear. An read or write of the Data register while BSY=1 or while BSY=0 DRQ=0 is ignored. See the I/O response tables. It has been this way since before ATA-1. Of course a host that performs reads or writes under these device status condition is a confused host. Unexpected host read/write accesses that could indicate a confused host is an area T13 just does want to address (so far) but I think the day is approaching fast when something will need to be done. The most dangerous of all these is the host that writes the Command register while BSY=1 or BSY=0 DRQ=1 (except that stupid DEVICE RESET thing). I want the standards to say that if a device detects this (an the detection logic can be optional, but if implemented) the device shall immediately have status of BSY=0 DRQ=0 ERR=1 ABRT=1 and IDNF=1 with no assertion of INTRQ. The device shall continue to have this status until a H/W or S/W reset (or DEVICE RESET) is received. Maybe the same thing should apply to an unexpected read/write of the Data register during a PIO data transfer command? ===================END FORWARDED MESSAGE=================== *** Hale Landis *** [EMAIL PROTECTED] *** *** Niwot, CO USA *** www.ata-atapi.com *** Subscribe/Unsubscribe instructions can be found at www.t13.org.
