This message is from the T13 list server.
On Thu, 06 Dec 2001 17:43:18 -0700, Pat LaVarre wrote: >Anyone out there able to resolve easily the apparent paradox >between these short extracts from Jim's & Hale's remarks? Jim was talking about the text in the Data register descripion. That text is: ! 7.6.4 Effect ! PIO out data transfers are processed by a series of ! reads to this register, each read transferring the ! data that follows the previous read. PIO in data ! transfers are processed by a series of writes to this ! register, each write transferring the data that follows ! the previous write. The results of a read during a PIO ! in or a write during a PIO out are indeterminate. Jim is correct... The last sentence is incorrect... The in and out directions are reversed. I wonder how long this has been wrong? But remember the I/O R/W response tables have higher priority than this text and the tables are more complete and are correct. And I (Hale said): >An read or write of the Data register while BSY=1 or while BSY=0 >DRQ=0 is ignored. See the I/O response tables. It has been this way >since before ATA-1. I was just pointing out that the basic rules for how and when the Data register is accessed have not changed since the rules were first established (prior to ATA-1). What may confuse some people is the fact that many of these rules were never stated in a standards document until the I/O R/W response tables were added. *** Hale Landis *** [EMAIL PROTECTED] *** *** Niwot, CO USA *** www.ata-atapi.com *** Subscribe/Unsubscribe instructions can be found at www.t13.org.
