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There is no contradiction.  Note that in the case of READing if the device
"ignores" an improper PIO, then what physically happens is that the host
will latch the data bus with whatever happens to be out there (since the
device made no special attempt to put anything on the bus, and there is no
interlock between the host and device on a single PIO read).  Whatever
happens to be out there is, of course, indeterminate unless you have
specific prior knowledge of what was happening on the bus.

On writes the host information is ignored by the device, which in turn
results in an indeterminate behaviour (once again, specific to context).

Bottom line is that in PIO if the host wants to do something, then
physically something WILL happen.  But the results can be indeterminate if
the device does properly understand what is going on or ignores what is
going on.

Jim


-----Original Message-----
From: Pat LaVarre [mailto:[EMAIL PROTECTED]]
Sent: Thursday, December 06, 2001 4:43 PM
To: [EMAIL PROTECTED]
Subject: Re: [t13] Re: unexpected data clocks


This message is from the T13 list server.


Anyone out there able to resolve easily the apparent paradox between these
short extracts from Jim's & Hale's remarks?

>>> "Mcgrath, Jim" <[EMAIL PROTECTED]> 12/06/01 12:14PM >>>
...

In ATA-6 r 3, section 7.6.4 (Effect of the Data Register), it states that: 
... The results of a read during a PIO in or a write during a PIO out are
indeterminate."

So the case is covered, although documented incorrectly (note: the sense of
DATA-IN and DATA-OUT are reversed in the above text, so that should be
corrected).
...

>>> [EMAIL PROTECTED] 12/06/01 12:45PM >>>
On Thu, 06 Dec 2001 10:54:58 -0700, Pat LaVarre wrote:
>For Pio I guess I think of this as a special case of 
>how to respond to Pio r/w of the x1F0 Data register 
>at times when DRQ is clear.

An read or write of the Data register while BSY=1 or while BSY=0
DRQ=0 is ignored. See the I/O response tables. It has been this way
since before ATA-1.
...

Maybe the same thing should apply to an unexpected read/write of the
Data register during a PIO data transfer command?
...


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