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On Mon, 17 Dec 2001 09:54:06 -0700, Pat LaVarre wrote: >Let's try the example Scsi Cdb of x 2A 0 00:00:00:00 0 00:12 0 >i.e. a write of the x12 blocks at Lba 0. >If, out of band, the host and device have mutually agreed that >each block contains x200 bytes, then yes only a Bad Host will >move out more than x12 * x200 = x2400 bytes. OK so far. >But now let's suppose the Bad Media refuses to let the device >move more than 3 blocks. And let's suppose our device, in >Pio/SwDmw/MwDma modes, accordingly moves just 4 * x200 = x800 >bytes and then stops the transfer. Do you mean "pause" or "stop" (stop as in the command is about to end with "error" status)?. If you mean "stop" because the device is about to declare that the command has failed due to an error condition then there is no problem. ATA/ATAPI rules says the ENTIRE command must be retried. If you mean "pause" then I assume you are making the BIG assumption that even in PIO mode the device can control the size of DRQ data blocks such that these blocks can be made to line up with the media block size? (In my opinion an ATAPI interface chip that attempted to align DRQ data blocks with media data blocks would be unnecessarily complex and would be doing something not required on an ATAPI device.) >If we change to use merely standard Atapi UDma, now we see a >difference. Rather than x800 of x2400 bytes moving out, when >connected at UDma33, we see as many as x804 bytes move out. So what? Again if you mean "stop" then none of the data is "valid" and the ENTIRE command must be retried. If you mean "pause" then there is still no problem here. The device has just received the first four bytes of the next sector. In my opinion a properly designed ATAPI interface chip would understand this and would be very happy to receive the remaining x7fc bytes of this sector once the "pause" condition went away. Where/what is the problem here? Since a device, even an ATA device, can not control when a host side will pause a DMA data burst or even when a host side will terminate a DMA burst, these things can happen at any time and at any place within the DMA data transfer for a command. I would guess these happen more frequently at places that do not align with a media block boundary than when they do align. There is no excuse for an ATA or ATAPI interface chip that implements DMA (MW or U-DMA) to not handle this correctly. As for X-to-ATA/ATAPI bridge devices, well..., they better handle it properly too otherwise they are not properly implemented ATA/ATAPI host devices. And I would even go so far as to say that if some condition happened that the bridge device could not handle then the bridge device may have to "fake" an error to its host (even when there was no error on the ATA/ATAPI side) just to maintain the proper execution of the commands on the X interface side. *** Hale Landis *** [EMAIL PROTECTED] *** *** Niwot, CO USA *** www.ata-atapi.com *** Subscribe/Unsubscribe instructions can be found at www.t13.org.
