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Hi Sergei, Since the new ADMA is a MMIO core and not IOMIO, you are required an new subclass ident. Whereas BAR4 is an PCI IO_MASK under SFF-8038i rules and the new Intel doc e02105r0, ADMA uses and extended MMIO at BAR4 and crosses BAR5. They are not the same transport layer. Cheers, Andre Hedrick CEO/President, LAD Storage Consulting Group Linux ATA Development Linux Disk Certification Project On Tue, 26 Feb 2002, Sergei Shtylyov wrote: > This message is from the T13 list server. > > > Hello, Michael. > > >The registers you enumerate (below) are decent for device capabilities > >detection, but putting an identification field as part of the ADMA memory > >mapped registers would be a more flexible "standard" method for determining > >if a controller meets this proposed standard. The id field is used in > other > >controller types, and would work fine here too. Another method is to > >require a new capabilities pointer, but this would only work for ADMA as a > >brand new device type unencumbered by the legacy ATA controller features. > > I don't see why should the new capability ID be introduced when the > device subclass itself identifies the ADMA (remember, it has sub-class > value 05h, not the legacy 01h, and the programming interface register > has the different meaning than that of legacy IDE subclass)? Or are there > (or will be) any other ADMA-incompatible devices using this subclass > value (Serial ATA controllers maybe)? Even if so, the discrimination can > be made basing on the programming interface register... > > PS: I have the same question about the revision ID--D1510 states that it > shall be equal 4xh. The specific values are used to judge whether ADMA > engine supports ATAPI devices or not? I suppose some other method > should be used to identify this... > > -- > Sergei Shtylyov > E-mail: [EMAIL PROTECTED] > FidoNet: 2:5020/118.24 > > > > > Subscribe/Unsubscribe instructions can be found at www.t13.org. > Subscribe/Unsubscribe instructions can be found at www.t13.org.
